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[86.13.91.161]) by smtp.gmail.com with ESMTPSA id n32sm21792267wms.1.2021.11.20.14.47.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 20 Nov 2021 14:47:00 -0800 (PST) Subject: Re: [PATCH v4 04/16] media: i2c: Support 19.2MHz input clock in ov8865 To: Sakari Ailus Cc: Paul Kocialkowski , linux-media@vger.kernel.org, Yong Zhi , Bingbu Cao , Tianshu Qiu , Andy Shevchenko , Hans de Goede , Laurent Pinchart , Kieran Bingham References: <20211101001119.46056-1-djrscally@gmail.com> <20211101001119.46056-5-djrscally@gmail.com> From: Daniel Scally Message-ID: <4e87d0d0-3eed-e464-ce16-e64cf6d89ab9@gmail.com> Date: Sat, 20 Nov 2021 22:46:59 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Hi Sakari - sorry, only just coming back to this series. On 01/11/2021 14:52, Sakari Ailus wrote: >> +static struct ov8865_pll_configs ov8865_pll_configs_19_2mhz = { >> + .pll1_config = &ov8865_pll1_config_native_19_2mhz, >> + .pll2_config_native = &ov8865_pll2_config_native_19_2mhz, >> + .pll2_config_binning = &ov8865_pll2_config_binning_19_2mhz, >> +}; >> + >> +static struct ov8865_pll_configs ov8865_pll_configs_24mhz = { >> + .pll1_config = &ov8865_pll1_config_native_24mhz, >> + .pll2_config_native = &ov8865_pll2_config_native_24mhz, >> + .pll2_config_binning = &ov8865_pll2_config_binning_24mhz, >> +}; > > These should be const. Done, thank you. >> @@ -2858,13 +2917,38 @@ static int ov8865_probe(struct i2c_client *client) >> goto error_endpoint; >> } >> >> - rate = clk_get_rate(sensor->extclk); >> - if (rate != OV8865_EXTCLK_RATE) { >> - dev_err(dev, "clock rate %lu Hz is unsupported\n", rate); >> + /* >> + * We could have either a 24MHz or 19.2MHz clock rate. Check for a >> + * clock-frequency property and if found, set that rate. This should >> + * cover the ACPI case. If the system uses devicetree then the >> + * configured rate should already be set, so we'll have to check it. >> + */ >> + ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency", >> + &rate); >> + if (!ret) { >> + ret = clk_set_rate(sensor->extclk, rate); >> + if (ret) { >> + dev_err(dev, "failed to set clock rate\n"); >> + return ret; >> + } >> + } >> + >> + sensor->extclk_rate = clk_get_rate(sensor->extclk); > > clk_get_rate() returns 0 if you don't have a clock. But you can still have > clock-frequency property that tells the frequency. This is generally the > case on ACPI based systems apart from some exceptions (which I understand > you're well aware of). > > See e.g. drivers/media/i2c/ccs/ccs-core.c . I'm checking the clock-frequency property above...that should be sufficient here I think right? >> + >> + for (i = 0; i < ARRAY_SIZE(supported_extclk_rates); i++) { >> + if (sensor->extclk_rate == supported_extclk_rates[i]) >> + break; >> + } >> + >> + if (i == ARRAY_SIZE(supported_extclk_rates)) { >> + dev_err(dev, "clock rate %lu Hz is unsupported\n", >> + sensor->extclk_rate); >> ret = -EINVAL; >> goto error_endpoint; >> } >> >> + sensor->pll_configs = ov8865_pll_configs[i]; >> + >> /* Subdev, entity and pad */ >> >> subdev = &sensor->subdev; >