Re: s5p-fimc capturing interlaced BT656

[Sylwester Nawrocki <sylvester.nawrocki@gmail.com>]

On 08/03/2012 10:01 PM, Mike Dyer wrote:
> I have indeed tried setting that, but with no effect.  However, checking
> through the datasheet for the FIMC I discovered a DMA output (CIOCTRL)
> register bit called 'Weave_Out'. The description is:
> 
> "Even and Odd fields can be weaved together and combined to form a
> complete progressive frame by hardware. This field is useful for
> interlace DMA output mode (Interlace_out or CAM_INTERLACE). Even field
> address (1st frame start address) is used weave address. Odd fields
> address (2nd frame start address) is ignored."
> 
> This does produce full sized frames, but I still seem to only be getting
> one field per frame, with a blank line inserted between each real line.
> Setting both interlace and weave doesn't seem to help. So, something
> still missing...
> 
> I wonder if the irq handler is getting called for each field, maybe we
> need to wait for two interrupts before dequeing the frame?

Hmm, might be worth to try. But I'm wondering if the output DMA handling
doesn't need to be reworked for that. According to the datasheet (Figure 
2-20 Frame Buffer Control), even fields are written to DMA buffer with 
even index (e.g. 0) and odd fields are written to DMA buffer with odd 
index (e.g. 1). So possibly, if we set same address at two DMA buffer 
start address registers (e.g. FIMC_REG_CIOYSA(0), FIMC_REG_CIOYSA(1)) 
then even and odd frame will be written to proper memory location ?

This might not be very difficult to implement.

--

Regards,
Sylwester