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[88.112.131.206]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2f40484c31dsm7430811fa.90.2024.08.24.06.19.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 24 Aug 2024 06:19:06 -0700 (PDT) Message-ID: <5a91ea63-2229-4c21-8caa-ca0912b1b8da@linaro.org> Date: Sat, 24 Aug 2024 16:19:05 +0300 Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 12/13] media: qcom: camss: Add CSID Gen3 support for sm8550 Content-Language: en-US To: Depeng Shao , rfoss@kernel.org, todor.too@gmail.com, bryan.odonoghue@linaro.org, mchehab@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@quicinc.com, Yongsheng Li References: <20240812144131.369378-1-quic_depengs@quicinc.com> <20240812144131.369378-13-quic_depengs@quicinc.com> From: Vladimir Zapolskiy In-Reply-To: <20240812144131.369378-13-quic_depengs@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 8/12/24 17:41, Depeng Shao wrote: > The CSID in sm8550 is gen3, it has new register offset and new > functionality. The buf done irq,register update and reset are > moved to CSID gen3. > > The sm8550 also has a new block is named as CSID top, CSID can > connect to VFE or SFE(Sensor Front End), the connection is controlled > by CSID top. > > Co-developed-by: Yongsheng Li > Signed-off-by: Yongsheng Li > Signed-off-by: Depeng Shao > --- > drivers/media/platform/qcom/camss/Makefile | 1 + > .../platform/qcom/camss/camss-csid-gen3.c | 339 ++++++++++++++++++ > .../platform/qcom/camss/camss-csid-gen3.h | 26 ++ > .../media/platform/qcom/camss/camss-csid.c | 46 ++- > .../media/platform/qcom/camss/camss-csid.h | 10 + > drivers/media/platform/qcom/camss/camss.c | 91 +++++ > drivers/media/platform/qcom/camss/camss.h | 2 + > 7 files changed, 503 insertions(+), 12 deletions(-) > create mode 100644 drivers/media/platform/qcom/camss/camss-csid-gen3.c > create mode 100644 drivers/media/platform/qcom/camss/camss-csid-gen3.h > > diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile > index e636968a1126..c336e4c1a399 100644 > --- a/drivers/media/platform/qcom/camss/Makefile > +++ b/drivers/media/platform/qcom/camss/Makefile > @@ -7,6 +7,7 @@ qcom-camss-objs += \ > camss-csid-4-1.o \ > camss-csid-4-7.o \ > camss-csid-gen2.o \ > + camss-csid-gen3.o \ > camss-csiphy-2ph-1-0.o \ > camss-csiphy-3ph-1-0.o \ > camss-csiphy.o \ > diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/media/platform/qcom/camss/camss-csid-gen3.c > new file mode 100644 > index 000000000000..d96bc126f0a9 > --- /dev/null > +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c > @@ -0,0 +1,339 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * camss-csid-gen3.c > + * > + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module > + * > + * Copyright (c) 2024 Qualcomm Technologies, Inc. > + */ > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "camss.h" > +#include "camss-csid.h" > +#include "camss-csid-gen3.h" > + > +#define CSID_TOP_IO_PATH_CFG0(csid) (0x4 * (csid)) > +#define OUTPUT_IFE_EN 0x100 > +#define INTERNAL_CSID 1 > + > +#define CSID_RST_CFG 0xC > +#define RST_MODE 0 > +#define RST_LOCATION 4 > + > +#define CSID_RST_CMD 0x10 > +#define SELECT_HW_RST 0 > +#define SELECT_SW_RST 1 > +#define SELECT_IRQ_RST 2 > + > +#define CSID_CSI2_RX_IRQ_STATUS 0x9C > +#define CSID_CSI2_RX_IRQ_MASK 0xA0 > +#define CSID_CSI2_RX_IRQ_CLEAR 0xA4 > +#define CSID_CSI2_RX_IRQ_SET 0xA8 > + > +#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) (0xEC + 0x10 * (rdi)) > + > +#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) (0xF4 + 0x10 * (rdi)) > +#define CSID_CSI2_RDIN_IRQ_SET(rdi) (0xF8 + 0x10 * (rdi)) > + > +#define CSID_TOP_IRQ_STATUS 0x7C The list of macros shall be sorted by register offset value. > +#define TOP_IRQ_STATUS_RESET_DONE 0 > + > +#define CSID_TOP_IRQ_MASK 0x80 > +#define CSID_TOP_IRQ_CLEAR 0x84 > +#define CSID_TOP_IRQ_SET 0x88 > + > +#define CSID_IRQ_CMD 0x14 > +#define IRQ_CMD_CLEAR 0 > +#define IRQ_CMD_SET 4 > + > +#define CSID_REG_UPDATE_CMD 0x18 > + > +#define CSID_BUF_DONE_IRQ_STATUS 0x8C > +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ? 1 : 14) > +#define CSID_BUF_DONE_IRQ_MASK 0x90 > +#define CSID_BUF_DONE_IRQ_CLEAR 0x94 > +#define CSID_BUF_DONE_IRQ_SET 0x98 > + > +#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 > + > +#define CSID_CSI2_RX_CFG0 0x200 > +#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0 > +#define CSI2_RX_CFG0_DL0_INPUT_SEL 4 > +#define CSI2_RX_CFG0_PHY_NUM_SEL 20 > + > +#define CSID_CSI2_RX_CFG1 0x204 > +#define CSI2_RX_CFG1_ECC_CORRECTION_EN 0 > +#define CSI2_RX_CFG1_VC_MODE 2 > + > +#define CSID_RDI_CFG0(rdi) (0x500 + 0x100 * (rdi)) > +#define RDI_CFG0_TIMESTAMP_EN 6 > +#define RDI_CFG0_TIMESTAMP_STB_SEL 8 > +#define RDI_CFG0_DECODE_FORMAT 12 > +#define RDI_CFG0_DT 16 > +#define RDI_CFG0_VC 22 > +#define RDI_CFG0_DT_ID 27 > +#define RDI_CFG0_EN 31 > + > +#define CSID_RDI_CFG1(rdi) (0x510 + 0x100 * (rdi)) > +#define RDI_CFG1_DROP_H_EN 5 > +#define RDI_CFG1_DROP_V_EN 6 > +#define RDI_CFG1_CROP_H_EN 7 > +#define RDI_CFG1_CROP_V_EN 8 > +#define RDI_CFG1_PIX_STORE 10 > +#define RDI_CFG1_PACKING_FORMAT 15 > + > +#define CSID_RDI_CTRL(rdi) (0x504 + 0x100 * (rdi)) Sorted by register offset please. > +#define RDI_CTRL_START_CMD 0 > + > +#define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi) (0x548 + 0x100 * (rdi)) > +#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (0x54C + 0x100 * (rdi)) > + > +static inline int reg_update_rdi(struct csid_device *csid, int n) > +{ > + return BIT(n + 4) + BIT(20 + n); Taking as unshifted bit BIT(4) is RUP and BIT(20) is AUP, add corresponding macros for them, then return (... | ...) << n; > +} > +#define REG_UPDATE_RDI reg_update_rdi > + -- Best wishes, Vladimir