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From: Heiko =?ISO-8859-1?Q?St=FCbner?= <heiko@sntech.de>
To: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org
Cc: liujianfeng1994@gmail.com, Jianfeng Liu <liujianfeng1994@gmail.com>
Subject:
 Re: [PATCH 2/3] arm64: dts: rockchip: Add Hantro G1 VPU support for RK3588
Date: Thu, 28 Dec 2023 00:12:48 +0100
Message-ID: <6924598.K2JlShyGXD@diego>
In-Reply-To: <20231227173911.3295410-3-liujianfeng1994@gmail.com>
References:
 <20231227173911.3295410-1-liujianfeng1994@gmail.com>
 <20231227173911.3295410-3-liujianfeng1994@gmail.com>
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Hi,

Am Mittwoch, 27. Dezember 2023, 18:39:10 CET schrieb Jianfeng Liu:
> This patch enables Hantro G1 video decoder in RK3588's
> device-tree
> 
> Tested with FFmpeg v4l2_request code taken from [1]
> with MPEG2, H.264 and VP8 samples.
> 
> [1] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch
> 
> Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> index 5fb0baf8a..b3536e097 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> @@ -708,6 +708,26 @@ vop_mmu: iommu@fdd97e00 {
>  		status = "disabled";
>  	};
> 
> +	vpu: video-codec@fdb50400 {

please sort nodes by bus-address. According to the current rk3588s.dtsi,
both nodes should be between 
- i2c@fd880000
+ video-codec@fdb50400
+ iommu@fdb50800
- vop@fdd90000


Otherwise this looks nice :-) .

Thanks
Heiko

> +		compatible = "rockchip,rk3588-vpu";
> +		reg = <0x0 0xfdb50000 0x0 0x800>;
> +		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
> +		clock-names = "aclk", "hclk";
> +		iommus = <&vdpu_mmu>;
> +		power-domains = <&power RK3588_PD_VDPU>;
> +	};
> +
> +	vdpu_mmu: iommu@fdb50800 {
> +		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> +		reg = <0x0 0xfdb50800 0x0 0x40>;
> +		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clock-names = "aclk", "iface";
> +		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
> +		power-domains = <&power RK3588_PD_VDPU>;
> +		#iommu-cells = <0>;
> +	};
> +
>  	uart0: serial@fd890000 {
>  		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
>  		reg = <0x0 0xfd890000 0x0 0x100>;
> --
> 2.34.1
> 
> 
> _______________________________________________
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>