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Tue, 24 Jun 2025 16:11:42 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 55OGBfKb026366 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 24 Jun 2025 16:11:41 GMT Received: from [10.50.56.215] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 24 Jun 2025 09:11:38 -0700 Message-ID: <85137a8e-45be-3bb2-d094-79754fa2a8be@quicinc.com> Date: Tue, 24 Jun 2025 21:41:35 +0530 Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 1/5] dt-bindings: media: qcom,sm8550-iris: add non_pixel and resv_region properties Content-Language: en-US To: Dmitry Baryshkov CC: Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , References: <20250620-video_cb-v1-0-9bcac1c8800c@quicinc.com> <20250620-video_cb-v1-1-9bcac1c8800c@quicinc.com> From: Vikash Garodia In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=NdDm13D4 c=1 sm=1 tr=0 ts=685ace3e cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=jL3G2h9b1PvCzNpYu-UA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDEzNSBTYWx0ZWRfXw2Q6T2Cq/zSi xzNFh7wP9iitFjtnknc1VvzavBGZaRi+va7DbOOOTgo5oRTVpxLYfFmAcMH3jC3CDgI3/sQnISY 5pAc66xzI3oH4M06qYsm0DsYuT79zUHB7b2vuyraiu7ihA34WCKtrsaZciBl4/vEeCe/M6JFRlh TpkSV9tkkXGGugcBphurYQTIpfscHQcVlvZZ/EKhhvIgTAON0pT6+x8x69JSlVbgZWHS6Lfy6JX ZZaKMiQvlX51jRAjSwKgCpU4cXTH3jleDL1N0/9EtBhKeNnzmUTotAegooEvIquBdhgdWJlZuJL BqkS6bn/eiW92V99UrSUk7QOqm640xyaC4oNsaeAsyVMPzWm8tkslnxHEUgN8A8tOx8GhIrw7Yr MUlHBObaU2TfCi6xRLR5gqfMmroEDCJzkrvtUAAHBr0xxCC6XNkVrtaxugq95F1Wjrm48kD6 X-Proofpoint-ORIG-GUID: dr1aNnrTRTsCdJ-ir-BW0e_zAtusX9U5 X-Proofpoint-GUID: dr1aNnrTRTsCdJ-ir-BW0e_zAtusX9U5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_06,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=823 adultscore=0 clxscore=1015 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240135 On 6/21/2025 3:09 AM, Dmitry Baryshkov wrote: > On Fri, Jun 20, 2025 at 11:50:51AM +0530, Vikash Garodia wrote: >> Existing definition limits the IOVA to an addressable range of 4GiB, and >> even within that range, some of the space is used by IO registers, >> thereby limiting the available IOVA to even lesser. Video hardware is >> designed to emit different stream-ID for pixel and non_pixel buffers, >> thereby introduce a non_pixel sub node to handle non_pixel stream-ID. >> >> With this, both iris and non_pixel device can have IOVA range of 0-4GiB >> individually. Certain video usecases like higher video concurrency needs >> IOVA higher than 4GiB. >> >> Add the "resv_region" property, which defines reserved IOVA regions that >> are *excluded* from addressable range. Video hardware generates >> different stream IDs based on the range of IOVA addresses. Thereby IOVA >> addresses for firmware and data buffers need to be non overlapping. For >> ex. 0x0-0x25800000 address range is reserved for firmware stream-ID, >> while non_pixel (bitstream ) stream-ID can be generated by hardware only >> when bitstream buffers IOVA address is from 0x25800000-0xe0000000. >> >> Signed-off-by: Vikash Garodia >> --- >> .../bindings/media/qcom,sm8550-iris.yaml | 35 ++++++++++++++++++++++ >> 1 file changed, 35 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml >> index c79bf2101812d83b99704f38b7348a9f728dff44..a1e83bae3c36f3a4c58b212ef457905e38091b97 100644 >> --- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml >> +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml >> @@ -65,10 +65,45 @@ properties: >> - const: core >> >> iommus: >> + minItems: 1 >> maxItems: 2 >> >> dma-coherent: true >> >> + resv_region: > > Ugh. Underscores... ACK > >> + type: object >> + additionalProperties: false >> + >> + description: >> + Reserve region specifies regions which should be excluded from IOVA. >> + >> + properties: >> + iommu-addresses: > > Missing type / ref. Also they are only described for reserved memory > regions. yes, looks like we can drop them from iris schema and rather reference it from reserved-memory schema. Awaiting comments on the ongoing discussion here [1] [1] https://lore.kernel.org/all/4c6233d9-be7b-baf3-fb05-3ea007e35330@quicinc.com/ > >> + minItems: 1 >> + maxItems: 4 >> + >> + required: >> + - iommu-addresses >> + >> + non_pixel: >> + type: object >> + additionalProperties: false > > > I still think that these usecases should be described with iommu-maps > rather than subnodes. You have a limited set of usecases: "non-pixel", > secure buffers, etc. Define an ID for each of those and then allocate a > subdevice internally, mapping it to a corresponding set of IOMMUs. In secure buffers category, there would be 3 categories - pixel/non-pixel/internal. Adding it up with non secure, we would be having 4 sub nodes eventually. Reading about the usage of iommu-maps, I see there are below limitations. If you could suggest a way to handle these, 1. let say there are 4 stream-ids, iommu-maps does not provide a way to tell which stream-id is for which sub hardware block(device) within video, so that driver can use it for mapping the corresponding buffers. 2. defining the masks for different stream-ids. 3. IOVA address regions - Different stream-ids have non-mappable range, which i am specifying via iommu-addresses in sub nodes. Again, iommu-maps was invented for PCIe case where different stream-id can be routed to different iommus. In this case, all stream-id would be managed by same iommu. Regards, Vikash > >> + >> + description: >> + Non pixel context bank is needed when video hardware have distinct iommus >> + for non pixel buffers. > > What does non-pixel mean? Compressed data? > >> + >> + properties: >> + iommus: >> + maxItems: 1 >> + >> + memory-region: >> + maxItems: 1 >> + >> + required: >> + - iommus >> + - memory-region >> + >> operating-points-v2: true >> >> opp-table: >> >> -- >> 2.34.1 >> >