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bh=yPqgb82RV5Eh4di0p99++tt4PTXyauGdKJYgPKVgVkw=; b=bMRNtHrTdtXyip9IgAG/87kFux8hrvKvIyVVkK4rTjddnJCgjV7/VvqodbfSOmbeFgDN7r gOR4J9InWsRbIAibyYjrCTbWpH02z8hR6/0O/7aGeg2C7oBd1vrVVGAMJxKdUj6IuEB9m1 kO5ZmvQzDG3y1/yw4Au0LnpvzqYIkPqtn89hLSfh0rmujsPEDHF+vp5ufVvC+11qmUfNvE BIRBcjZb/UyXd2GlBfiajECikuzA58XBzf1kg7jiJm4dqYMBgEtwnIZcbGhjPK8+rOuCOf wn8ZG3a7iRFdJba2ws9HyH6GEE9sRc8e1RJLRLn/TPPQbrlrgZ5vSLlGpQx9ug== From: Miquel Raynal To: Keguang Zhang via B4 Relay Cc: Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , keguang.zhang@gmail.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-media@vger.kernel.org Subject: Re: [PATCH v12 2/2] mtd: rawnand: Add Loongson-1 NAND Controller Driver In-Reply-To: <20250121-loongson1-nand-v12-2-53507999de39@gmail.com> (Keguang Zhang via's message of "Tue, 21 Jan 2025 18:27:34 +0800") References: <20250121-loongson1-nand-v12-0-53507999de39@gmail.com> <20250121-loongson1-nand-v12-2-53507999de39@gmail.com> User-Agent: mu4e 1.12.7; emacs 29.4 Date: Thu, 06 Feb 2025 18:17:15 +0100 Message-ID: <87tt972dt0.fsf@bootlin.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeefvddrtddtgddvieeliecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvvefujghffgffkfggtgfgsehtqhertddtreejnecuhfhrohhmpefoihhquhgvlhcutfgrhihnrghluceomhhiqhhuvghlrdhrrgihnhgrlhessghoohhtlhhinhdrtghomheqnecuggftrfgrthhtvghrnhepffeghfejtdefieeguddukedujeektdeihfelleeuieeuveehkedvleduheeivdefnecukfhppeeltddrkeelrdduieefrdduvdejnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehinhgvthepledtrdekledrudeifedruddvjedphhgvlhhopehlohgtrghlhhhoshhtpdhmrghilhhfrhhomhepmhhiqhhuvghlrdhrrgihnhgrlhessghoohhtlhhinhdrtghomhdpnhgspghrtghpthhtohepuddupdhrtghpthhtohepuggvvhhnuhhllhdokhgvghhurghnghdriihhrghnghdrghhmrghilhdrtghomheskhgvrhhnvghlrdhorhhgpdhrtghpthhtoheprhhitghhrghrugesnhhougdrrghtpdhrtghpthhtohepvhhighhnvghshhhrsehtihdrtghomhdprhgtphhtthhopehrohgshheskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepkhhriihkodgutheskhgvrhhnvghlrdhorhhgpdhrtghpthhto heptghonhhorhdoughtsehkvghrnhgvlhdrohhrghdprhgtphhtthhopehkvghguhgrnhhgrdiihhgrnhhgsehgmhgrihhlrdgtohhmpdhrtghpthhtoheplhhinhhugidqmhhtugeslhhishhtshdrihhnfhhrrgguvggrugdrohhrgh X-GND-Sasl: miquel.raynal@bootlin.com Hello, > +static inline int ls1x_nand_check_op(struct nand_chip *chip, const > struct nand_operation *op) No inline function in a c file. > +{ > + struct ls1x_nand_host *host =3D nand_get_controller_data(chip); > + const struct nand_op_instr *instr1 =3D NULL, *instr2 =3D NULL; > + int op_id; > + > + for (op_id =3D 0; op_id < op->ninstrs; op_id++) { > + const struct nand_op_instr *instr =3D &op->instrs[op_id]; > + > + if (instr->type =3D=3D NAND_OP_CMD_INSTR) { > + if (!instr1) > + instr1 =3D instr; > + else if (!instr2) > + instr2 =3D instr; > + else > + break; > + } > + } > + > + if (!instr1 || !instr2) > + return 0; Is this expected? > + > + if (instr1->ctx.cmd.opcode =3D=3D NAND_CMD_RNDOUT && > + instr2->ctx.cmd.opcode =3D=3D NAND_CMD_RNDOUTSTART) > + return 0; > + > + if (instr1->ctx.cmd.opcode =3D=3D NAND_CMD_READ0 && > + instr2->ctx.cmd.opcode =3D=3D NAND_CMD_READSTART) > + return 0; > + > + if (instr1->ctx.cmd.opcode =3D=3D NAND_CMD_ERASE1 && > + instr2->ctx.cmd.opcode =3D=3D NAND_CMD_ERASE2) > + return 0; > + > + if (instr1->ctx.cmd.opcode =3D=3D NAND_CMD_SEQIN && > + instr2->ctx.cmd.opcode =3D=3D NAND_CMD_PAGEPROG) > + return 0; > + > + dev_err(host->dev, "unsupported opcode sequence: %x %x", > + instr1->ctx.cmd.opcode, instr2->ctx.cmd.opcode); > + > + return -EOPNOTSUPP; > +} > + > +static int ls1x_nand_exec_op(struct nand_chip *chip, > + const struct nand_operation *op, > + bool check_only) > +{ > + int ret; > + if (check_only) ? > + ret =3D ls1x_nand_check_op(chip, op); > + if (ret) > + return ret; > + > + return nand_op_parser_exec_op(chip, &ls1x_nand_op_parser, op, check_onl= y); > +} > + > +static const char * const nand_ecc_algos[] =3D { > + [NAND_ECC_ALGO_UNKNOWN] =3D "none", > + [NAND_ECC_ALGO_HAMMING] =3D "hamming", > + [NAND_ECC_ALGO_BCH] =3D "bch", > +}; No way you need this in your driver :-) Thanks, Miqu=C3=A8l