* [PATCH v1 0/4] Adding capture support for DM365 device
@ 2009-08-17 20:05 neilsikka
2009-08-17 20:05 ` [PATCH v1 1/4] DM365 Platform support for VPFE neilsikka
0 siblings, 1 reply; 8+ messages in thread
From: neilsikka @ 2009-08-17 20:05 UTC (permalink / raw)
To: linux-media, davinci-linux-open-source; +Cc: khilman, hverkuil, Neil Sikka
From: Neil Sikka <neilsikka@ti.com>
This patch series adds support for the VPSS capture on the DM365 SOC.
Specifically, it supports the CCDC/ISIF module. This code has been tested and
works with the TVP5146 decoder (using the tvp514x driver). During testing of
this code, the NTSC capture format was used. This patch depends on previous
other patches contributed by Muralidharan Karicheri. Please see the individual
patch notes for dependency details. The patches contained in this patch set are:
1) DM365 Platform support for VPFE-additions to the DM365 SOC files
2) DM365 VPSS support-additions to the VPSS.h and VPSS.c files
3) CCDC support on DM365-the actual DM365 CCDC driver and its supporting files
NOTE: All patches are to be applied before build.
Mandatory reviewers:
Hans Verkuil <hverkuil@xs4all.nl> for V4L tree
Kevin Hilman <khilman@deeprootsystems.com> for DaVinci tree
Reviewed-by: Muralidharan Karicheri <m-karicheri2@ti.com>
Signed-off-by: Neil Sikka <neilsikka@ti.com>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v1 1/4] DM365 Platform support for VPFE
2009-08-17 20:05 [PATCH v1 0/4] Adding capture support for DM365 device neilsikka
@ 2009-08-17 20:05 ` neilsikka
2009-08-17 20:05 ` [PATCH v1 2/4] DM365 VPSS support neilsikka
2009-10-15 23:18 ` [PATCH v1 1/4] DM365 Platform support for VPFE Kevin Hilman
0 siblings, 2 replies; 8+ messages in thread
From: neilsikka @ 2009-08-17 20:05 UTC (permalink / raw)
To: linux-media, davinci-linux-open-source; +Cc: khilman, hverkuil, Neil Sikka
From: Neil Sikka <neilsikka@ti.com>
This has platform and board setup changes to support the vpfe capture
driver for DM365 EVMs.
Reviewed-by: Muralidharan Karicheri <m-karicheri2@ti.com>
Mandatory-Reviewer: Hans Verkuil <hverkuil@xs4all.nl>
Mandatory-Reviewer: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Neil Sikka <neilsikka@ti.com>
---
Applies to Kevin Hilman's linux-davinci repository
arch/arm/mach-davinci/board-dm365-evm.c | 71 ++++++++++++++++++++++++++++
arch/arm/mach-davinci/dm365.c | 68 ++++++++++++++++++++++++++
arch/arm/mach-davinci/include/mach/dm365.h | 2 +
3 files changed, 141 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index f6adf79..757ad13 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -38,6 +38,8 @@
#include <mach/common.h>
#include <mach/mmc.h>
#include <mach/nand.h>
+#include <linux/videodev2.h>
+#include <media/tvp514x.h>
static inline int have_imager(void)
@@ -98,6 +100,11 @@ static inline int have_tvp7002(void)
static void __iomem *cpld;
+static struct tvp514x_platform_data tvp5146_pdata = {
+ .clk_polarity = 0,
+ .hs_polarity = 1,
+ .vs_polarity = 1
+};
/* NOTE: this is geared for the standard config, with a socketed
* 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
@@ -210,6 +217,68 @@ static int cpld_mmc_get_ro(int module)
return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
}
+#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
+/* Inputs available at the TVP5146 */
+static struct v4l2_input tvp5146_inputs[] = {
+ {
+ .index = 0,
+ .name = "Composite",
+ .type = V4L2_INPUT_TYPE_CAMERA,
+ .std = TVP514X_STD_ALL,
+ },
+ {
+ .index = 1,
+ .name = "S-Video",
+ .type = V4L2_INPUT_TYPE_CAMERA,
+ .std = TVP514X_STD_ALL,
+ },
+};
+
+/*
+ * this is the route info for connecting each input to decoder
+ * ouput that goes to vpfe. There is a one to one correspondence
+ * with tvp5146_inputs
+ */
+static struct vpfe_route tvp5146_routes[] = {
+ {
+ .input = INPUT_CVBS_VI2B,
+ .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
+ },
+{
+ .input = INPUT_SVIDEO_VI2C_VI1C,
+ .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
+ },
+};
+
+static struct vpfe_subdev_info vpfe_sub_devs[] = {
+{
+ .module_name = "tvp5146",
+ .grp_id = 0,
+ .num_inputs = ARRAY_SIZE(tvp5146_inputs),
+ .inputs = tvp5146_inputs,
+ .routes = tvp5146_routes,
+ .can_route = 1,
+ .ccdc_if_params = {
+ .if_type = VPFE_BT656,
+ .hdpol = VPFE_PINPOL_POSITIVE,
+ .vdpol = VPFE_PINPOL_POSITIVE,
+ },
+ .board_info = {
+ I2C_BOARD_INFO("tvp5146", 0x5d),
+ .platform_data = &tvp5146_pdata,
+ },
+ }
+};
+
+static struct vpfe_config vpfe_cfg = {
+ .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
+ .sub_devs = vpfe_sub_devs,
+ .card_name = "DM365 EVM",
+ .ccdc = "DM365 ISIF",
+ .num_clocks = 1,
+ .clocks = {"vpss_master"},
+};
+
static struct davinci_mmc_config dm365evm_mmc_config = {
.get_cd = cpld_mmc_get_cd,
.get_ro = cpld_mmc_get_ro,
@@ -461,6 +530,8 @@ static struct davinci_uart_config uart_config __initdata = {
static void __init dm365_evm_map_io(void)
{
+ /* setup input configuration for VPFE input devices */
+ dm365_set_vpfe_config(&vpfe_cfg);
dm365_init();
}
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index f8bac94..aa432d4 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -904,6 +904,62 @@ void __init dm365_init(void)
davinci_common_init(&davinci_soc_info_dm365);
}
+static struct resource dm365_vpss_resources[] = {
+ {
+ /* VPSS ISP5 Base address */
+ .name = "vpss",
+ .start = 0x01c70000,
+ .end = 0x01c70000 + 0xff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ /* VPSS CLK Base address */
+ .name = "vpss",
+ .start = 0x01c70200,
+ .end = 0x01c70200 + 0xff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device dm365_vpss_device = {
+ .name = "vpss",
+ .id = -1,
+ .dev.platform_data = "dm365_vpss",
+ .num_resources = ARRAY_SIZE(dm365_vpss_resources),
+ .resource = dm365_vpss_resources,
+};
+
+static struct resource vpfe_resources[] = {
+ {
+ .start = IRQ_VDINT0,
+ .end = IRQ_VDINT0,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = IRQ_VDINT1,
+ .end = IRQ_VDINT1,
+ .flags = IORESOURCE_IRQ,
+ },
+ /* ISIF Base address */
+ {
+ .start = 0x01c71000,
+ .end = 0x01c71000 + 0x1ff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
+static struct platform_device vpfe_capture_dev = {
+ .name = CAPTURE_DRV_NAME,
+ .id = -1,
+ .num_resources = ARRAY_SIZE(vpfe_resources),
+ .resource = vpfe_resources,
+ .dev = {
+ .dma_mask = &vpfe_capture_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
static int __init dm365_init_devices(void)
{
if (!cpu_is_davinci_dm365())
@@ -913,6 +969,18 @@ static int __init dm365_init_devices(void)
platform_device_register(&dm365_edma_device);
platform_device_register(&dm365_emac_device);
+ /*
+ * setup Mux configuration for vpfe input and register
+ * vpfe capture platform device
+ */
+ platform_device_register(&dm365_vpss_device);
+ platform_device_register(&vpfe_capture_dev);
+
return 0;
}
postcore_initcall(dm365_init_devices);
+
+void dm365_set_vpfe_config(struct vpfe_config *cfg)
+{
+ vpfe_capture_dev.dev.platform_data = cfg;
+}
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index 09db434..2fbead2 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -15,6 +15,7 @@
#include <linux/platform_device.h>
#include <mach/hardware.h>
+#include <media/davinci/vpfe_capture.h>
#include <mach/emac.h>
#define DM365_EMAC_BASE (0x01D07000)
@@ -25,5 +26,6 @@
#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000)
void __init dm365_init(void);
+void dm365_set_vpfe_config(struct vpfe_config *cfg);
#endif /* __ASM_ARCH_DM365_H */
--
1.6.0.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v1 2/4] DM365 VPSS support
2009-08-17 20:05 ` [PATCH v1 1/4] DM365 Platform support for VPFE neilsikka
@ 2009-08-17 20:05 ` neilsikka
2009-08-17 20:05 ` [PATCH v1 3/4] CCDC support on DM365 neilsikka
2009-10-15 23:18 ` [PATCH v1 1/4] DM365 Platform support for VPFE Kevin Hilman
1 sibling, 1 reply; 8+ messages in thread
From: neilsikka @ 2009-08-17 20:05 UTC (permalink / raw)
To: linux-media, davinci-linux-open-source; +Cc: khilman, hverkuil, Neil Sikka
From: Neil Sikka <neilsikka@ti.com>
This patch adds support for DM365 VPSS
Reviewed-by: Muralidharan Karicheri <m-karicheri2@ti.com>
Mandatory-Reviewer: Hans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: Neil Sikka <neilsikka@ti.com>
---
Applies to v4l-dvb linux-next repository
drivers/media/video/davinci/vpss.c | 232 ++++++++++++++++++++++++++++++++----
include/media/davinci/vpss.h | 59 +++++++++-
2 files changed, 268 insertions(+), 23 deletions(-)
diff --git a/drivers/media/video/davinci/vpss.c b/drivers/media/video/davinci/vpss.c
index 6d709ca..83dac1b 100644
--- a/drivers/media/video/davinci/vpss.c
+++ b/drivers/media/video/davinci/vpss.c
@@ -42,9 +42,12 @@ MODULE_AUTHOR("Texas Instruments");
/* masks and shifts */
#define VPSS_HSSISEL_SHIFT 4
-/*
+/* lock to write into common register */
+static spinlock_t vpss_lock;
+
+/**
* vpss operations. Depends on platform. Not all functions are available
- * on all platforms. The api, first check if a functio is available before
+ * on all platforms. The api, first check if a function is available before
* invoking it. In the probe, the function ptrs are intialized based on
* vpss name. vpss name can be "dm355_vpss", "dm644x_vpss" etc.
*/
@@ -53,14 +56,19 @@ struct vpss_hw_ops {
int (*enable_clock)(enum vpss_clock_sel clock_sel, int en);
/* select input to ccdc */
void (*select_ccdc_source)(enum vpss_ccdc_source_sel src_sel);
- /* clear wbl overlflow bit */
+ /* clear wbl overflow bit */
int (*clear_wbl_overflow)(enum vpss_wbl_sel wbl_sel);
+ /*set sync polarity */
+ void (*set_sync_pol)(struct vpss_sync_pol);
+ /*set the PG_FRAME_SIZE register*/
+ void (*set_pg_frame_size)(struct vpss_pg_frame_size);
};
/* vpss configuration */
struct vpss_oper_config {
- __iomem void *vpss_bl_regs_base;
- __iomem void *vpss_regs_base;
+ __iomem void *vpss_regs_base0;
+ __iomem void *vpss_regs_base1;
+ resource_size_t *vpss_regs_base2;
struct resource *r1;
resource_size_t len1;
struct resource *r2;
@@ -75,22 +83,32 @@ static struct vpss_oper_config oper_cfg;
/* register access routines */
static inline u32 bl_regr(u32 offset)
{
- return __raw_readl(oper_cfg.vpss_bl_regs_base + offset);
+ return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
}
static inline void bl_regw(u32 val, u32 offset)
{
- __raw_writel(val, oper_cfg.vpss_bl_regs_base + offset);
+ __raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
+}
+
+static inline u32 isp5_read(u32 offset)
+{
+ return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
+}
+
+static inline void isp5_write(u32 val, u32 offset)
+{
+ __raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
}
static inline u32 vpss_regr(u32 offset)
{
- return __raw_readl(oper_cfg.vpss_regs_base + offset);
+ return __raw_readl(oper_cfg.vpss_regs_base1 + offset);
}
static inline void vpss_regw(u32 val, u32 offset)
{
- __raw_writel(val, oper_cfg.vpss_regs_base + offset);
+ __raw_writel(val, oper_cfg.vpss_regs_base1 + offset);
}
static void dm355_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
@@ -98,12 +116,25 @@ static void dm355_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
bl_regw(src_sel << VPSS_HSSISEL_SHIFT, DM355_VPSSBL_CCDCMUX);
}
+static void dm365_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
+{
+ u32 temp = isp5_read(DM365_ISP5_CCDCMUX) & ~CCD_SRC_SEL_MASK;
+
+ /* if we are using pattern generator, enable it */
+ if (src_sel == VPSS_PGLPBK || src_sel == VPSS_CCDCPG)
+ temp |= 0x08;
+
+ temp |= (src_sel << CCD_SRC_SEL_SHIFT);
+ isp5_write(temp, DM365_ISP5_CCDCMUX);
+}
+
int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
{
if (!oper_cfg.hw_ops.select_ccdc_source)
return -1;
- dm355_select_ccdc_source(src_sel);
+ oper_cfg.hw_ops.select_ccdc_source(src_sel);
+
return 0;
}
EXPORT_SYMBOL(vpss_select_ccdc_source);
@@ -120,9 +151,56 @@ static int dm644x_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
mask = ~(mask << wbl_sel);
val = bl_regr(DM644X_SBL_PCR_VPSS) & mask;
bl_regw(val, DM644X_SBL_PCR_VPSS);
+
return 0;
}
+static void dm365_enable_irq(void)
+{
+ u32 current_val = isp5_read(DM365_VPSS_INTSEL1);
+ /*just enable INTSEL0 and INTSEL1 and leave everything else as is*/
+ current_val &= ~(CCD_INT_SEL_MASK);
+ current_val |= BIT_MASK(8);
+ isp5_write(current_val, DM365_VPSS_INTSEL1);
+}
+
+void dm365_set_sync_pol(struct vpss_sync_pol sync)
+{
+ int val = 0;
+ val = isp5_read(DM365_ISP5_CCDCMUX);
+
+ val |= (sync.ccdpg_hdpol << DM365_CCDC_PG_HD_POL_SHIFT);
+ val |= (sync.ccdpg_vdpol << DM365_CCDC_PG_VD_POL_SHIFT);
+
+ isp5_write(val, DM365_ISP5_CCDCMUX);
+}
+
+void vpss_set_sync_pol(struct vpss_sync_pol sync)
+{
+ if (!oper_cfg.hw_ops.set_sync_pol)
+ return;
+
+ oper_cfg.hw_ops.set_sync_pol(sync);
+}
+EXPORT_SYMBOL(vpss_set_sync_pol);
+
+void dm365_set_pg_frame_size(struct vpss_pg_frame_size frame_size)
+{
+ int current_reg = ((frame_size.hlpfr >> 1) - 1) << 16;
+
+ current_reg |= (frame_size.pplen - 1);
+ isp5_write(current_reg, DM365_ISP5_PG_FRAME_SIZE);
+}
+
+void vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size)
+{
+ if (!oper_cfg.hw_ops.set_pg_frame_size)
+ return;
+
+ oper_cfg.hw_ops.set_pg_frame_size(frame_size);
+}
+EXPORT_SYMBOL(vpss_set_pg_frame_size);
+
int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
{
if (!oper_cfg.hw_ops.clear_wbl_overflow)
@@ -132,7 +210,7 @@ int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
}
EXPORT_SYMBOL(vpss_clear_wbl_overflow);
-/*
+/**
* dm355_enable_clock - Enable VPSS Clock
* @clock_sel: CLock to be enabled/disabled
* @en: enable/disable flag
@@ -178,6 +256,93 @@ static int dm355_enable_clock(enum vpss_clock_sel clock_sel, int en)
vpss_regw(utemp, DM355_VPSSCLK_CLKCTRL);
spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);
+
+ return 0;
+}
+
+static int dm365_enable_clock(enum vpss_clock_sel clock_sel, int en)
+{
+ unsigned long flags;
+ u32 utemp, mask = 0x1, shift = 0, offset = DM365_PCCR;
+ u32 (*read)(u32 offset) = isp5_read;
+ void(*write)(u32 val, u32 offset) = isp5_write;
+
+ switch (clock_sel) {
+ case VPSS_BL_CLOCK:
+ break;
+ case VPSS_CCDC_CLOCK:
+ shift = 1;
+ break;
+ case VPSS_H3A_CLOCK:
+ shift = 2;
+ break;
+ case VPSS_RSZ_CLOCK:
+ shift = 3;
+ break;
+ case VPSS_IPIPE_CLOCK:
+ shift = 4;
+ break;
+ case VPSS_IPIPEIF_CLOCK:
+ shift = 5;
+ break;
+ case VPSS_PCLK_INTERNAL:
+ shift = 6;
+ break;
+ case VPSS_PSYNC_CLOCK_SEL:
+ shift = 7;
+ break;
+ case VPSS_VPBE_CLOCK:
+ read = vpss_regr;
+ write = vpss_regw;
+ offset = DM365_VPBE_CLK_CTRL;
+ break;
+ case VPSS_VENC_CLOCK_SEL:
+ shift = 2;
+ read = vpss_regr;
+ write = vpss_regw;
+ offset = DM365_VPBE_CLK_CTRL;
+ break;
+ case VPSS_LDC_CLOCK:
+ shift = 3;
+ read = vpss_regr;
+ write = vpss_regw;
+ offset = DM365_VPBE_CLK_CTRL;
+ break;
+ case VPSS_FDIF_CLOCK:
+ shift = 4;
+ read = vpss_regr;
+ write = vpss_regw;
+ offset = DM365_VPBE_CLK_CTRL;
+ break;
+ case VPSS_OSD_CLOCK_SEL:
+ shift = 6;
+ read = vpss_regr;
+ write = vpss_regw;
+ offset = DM365_VPBE_CLK_CTRL;
+ break;
+ case VPSS_LDC_CLOCK_SEL:
+ shift = 7;
+ read = vpss_regr;
+ write = vpss_regw;
+ offset = DM365_VPBE_CLK_CTRL;
+ break;
+ default:
+ printk(KERN_ERR "dm365_enable_clock: Invalid selector: %d\n",
+ clock_sel);
+ return -1;
+ }
+
+ spin_lock_irqsave(&vpss_lock, flags);
+ utemp = read(offset);
+ if (!en) {
+ mask = ~mask;
+ utemp &= (mask << shift);
+ } else
+ utemp |= (mask << shift);
+
+ write(utemp, offset);
+ spin_unlock_irqrestore(&vpss_lock, flags);
+
return 0;
}
@@ -192,7 +357,7 @@ EXPORT_SYMBOL(vpss_enable_clock);
static int __init vpss_probe(struct platform_device *pdev)
{
- int status, dm355 = 0;
+ int status, dm355 = 0, dm365 = 0;
if (!pdev->dev.platform_data) {
dev_err(&pdev->dev, "no platform data\n");
@@ -202,6 +367,8 @@ static int __init vpss_probe(struct platform_device *pdev)
if (!strcmp(oper_cfg.vpss_name, "dm355_vpss"))
dm355 = 1;
+ else if (!strcmp(oper_cfg.vpss_name, "dm365_vpss"))
+ dm365 = 1;
else if (strcmp(oper_cfg.vpss_name, "dm644x_vpss")) {
dev_err(&pdev->dev, "vpss driver not supported on"
" this platform\n");
@@ -220,13 +387,13 @@ static int __init vpss_probe(struct platform_device *pdev)
if (!oper_cfg.r1)
return -EBUSY;
- oper_cfg.vpss_bl_regs_base = ioremap(oper_cfg.r1->start, oper_cfg.len1);
- if (!oper_cfg.vpss_bl_regs_base) {
+ oper_cfg.vpss_regs_base0 = ioremap(oper_cfg.r1->start, oper_cfg.len1);
+ if (!oper_cfg.vpss_regs_base0) {
status = -EBUSY;
goto fail1;
}
- if (dm355) {
+ if (dm355 || dm365) {
oper_cfg.r2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!oper_cfg.r2) {
status = -ENOENT;
@@ -241,9 +408,9 @@ static int __init vpss_probe(struct platform_device *pdev)
goto fail2;
}
- oper_cfg.vpss_regs_base = ioremap(oper_cfg.r2->start,
+ oper_cfg.vpss_regs_base1 = ioremap(oper_cfg.r2->start,
oper_cfg.len2);
- if (!oper_cfg.vpss_regs_base) {
+ if (!oper_cfg.vpss_regs_base1) {
status = -EBUSY;
goto fail3;
}
@@ -252,9 +419,20 @@ static int __init vpss_probe(struct platform_device *pdev)
if (dm355) {
oper_cfg.hw_ops.enable_clock = dm355_enable_clock;
oper_cfg.hw_ops.select_ccdc_source = dm355_select_ccdc_source;
- } else
+ oper_cfg.hw_ops.set_sync_pol = NULL;
+ oper_cfg.hw_ops.set_pg_frame_size = NULL;
+ } else if (dm365) {
+ oper_cfg.hw_ops.enable_clock = dm365_enable_clock;
+ oper_cfg.hw_ops.select_ccdc_source = dm365_select_ccdc_source;
+ oper_cfg.hw_ops.set_sync_pol = dm365_set_sync_pol;
+ oper_cfg.hw_ops.set_pg_frame_size = dm365_set_pg_frame_size;
+
+ } else if (!strcmp(oper_cfg.vpss_name, "dm644x_vpss"))
oper_cfg.hw_ops.clear_wbl_overflow = dm644x_clear_wbl_overflow;
+ if (dm365)
+ dm365_enable_irq();
+
spin_lock_init(&oper_cfg.vpss_lock);
dev_info(&pdev->dev, "%s vpss probe success\n", oper_cfg.vpss_name);
return 0;
@@ -262,7 +440,7 @@ static int __init vpss_probe(struct platform_device *pdev)
fail3:
release_mem_region(oper_cfg.r2->start, oper_cfg.len2);
fail2:
- iounmap(oper_cfg.vpss_bl_regs_base);
+ iounmap(oper_cfg.vpss_regs_base0);
fail1:
release_mem_region(oper_cfg.r1->start, oper_cfg.len1);
return status;
@@ -270,12 +448,14 @@ fail1:
static int vpss_remove(struct platform_device *pdev)
{
- iounmap(oper_cfg.vpss_bl_regs_base);
+ iounmap(oper_cfg.vpss_regs_base0);
release_mem_region(oper_cfg.r1->start, oper_cfg.len1);
- if (!strcmp(oper_cfg.vpss_name, "dm355_vpss")) {
- iounmap(oper_cfg.vpss_regs_base);
+ if (!strcmp(oper_cfg.vpss_name, "dm355_vpss") ||
+ !strcmp(oper_cfg.vpss_name, "dm365_vpss")) {
+ iounmap(oper_cfg.vpss_regs_base1);
release_mem_region(oper_cfg.r2->start, oper_cfg.len2);
}
+
return 0;
}
@@ -290,11 +470,19 @@ static struct platform_driver vpss_driver = {
static void vpss_exit(void)
{
+ iounmap(oper_cfg.vpss_regs_base2);
+ release_mem_region(*oper_cfg.vpss_regs_base2, 4);
platform_driver_unregister(&vpss_driver);
}
static int __init vpss_init(void)
{
+ if (request_mem_region(VPSS_CLK_CTRL, 4, "vpss_clock_control")) {
+ oper_cfg.vpss_regs_base2 = ioremap(VPSS_CLK_CTRL, 4);
+ __raw_writel(0x18, oper_cfg.vpss_regs_base2);
+ } else
+ return -EBUSY;
+
return platform_driver_register(&vpss_driver);
}
subsys_initcall(vpss_init);
diff --git a/include/media/davinci/vpss.h b/include/media/davinci/vpss.h
index fcdff74..a8583a2 100644
--- a/include/media/davinci/vpss.h
+++ b/include/media/davinci/vpss.h
@@ -26,10 +26,41 @@
#ifndef _VPSS_H
#define _VPSS_H
+/* dm365 stuff or wutever like that */
+#define DM365_PCCR 0x04
+#define DM365_ISP_REG_BASE 0x01c70000
+#define DM365_VPSS_REG_BASE 0x01c70200
+#define DM365_VPBE_CLK_CTRL 0x00
+#define DM365_ISP5_CCDCMUX 0x20
+#define DM365_ISP5_PG_FRAME_SIZE 0x28
+#define DM365_CCDC_PG_VD_POL_SHIFT 0
+#define DM365_CCDC_PG_HD_POL_SHIFT 1
+#define DM365_VPSS_INTSEL1 0x10
+#define VPSS_CLK_CTRL 0x01C40044
+#define CCD_SRC_SEL_MASK (BIT_MASK(5) | BIT_MASK(4))
+#define CCD_SRC_SEL_SHIFT 4
+#define CCD_INT_SEL_MASK (BIT_MASK(12) | BIT_MASK(11)|\
+ BIT_MASK(10) | BIT_MASK(9) |\
+ BIT_MASK(8) | BIT_MASK(4) |\
+ BIT_MASK(3) | BIT_MASK(2) |\
+ BIT_MASK(1) | BIT_MASK(0))
+
/* selector for ccdc input selection on DM355 */
enum vpss_ccdc_source_sel {
VPSS_CCDCIN,
- VPSS_HSSIIN
+ VPSS_HSSIIN,
+ VPSS_PGLPBK,
+ VPSS_CCDCPG
+};
+
+struct vpss_sync_pol {
+ unsigned int ccdpg_hdpol:1;
+ unsigned int ccdpg_vdpol:1;
+};
+
+struct vpss_pg_frame_size {
+ short hlpfr;
+ short pplen;
};
/* Used for enable/diable VPSS Clock */
@@ -47,12 +78,38 @@ enum vpss_clock_sel {
*/
VPSS_VENC_CLOCK_SEL,
VPSS_VPBE_CLOCK,
+ /* DM365 only clocks */
+ VPSS_IPIPEIF_CLOCK,
+ VPSS_RSZ_CLOCK,
+ VPSS_BL_CLOCK,
+ /*
+ * When using VPSS_PCLK_INTERNAL in vpss_enable_clock() api
+ * following applies:-
+ * en = 0 disable internal PCLK
+ * en = 1 enables internal PCLK
+ */
+ VPSS_PCLK_INTERNAL,
+ /*
+ * When using VPSS_PSYNC_CLOCK_SEL in vpss_enable_clock() api
+ * following applies:-
+ * en = 0 enables MMR clock
+ * en = 1 enables VPSS clock
+ */
+ VPSS_PSYNC_CLOCK_SEL,
+ VPSS_LDC_CLOCK_SEL,
+ VPSS_OSD_CLOCK_SEL,
+ VPSS_FDIF_CLOCK,
+ VPSS_LDC_CLOCK
};
/* select input to ccdc on dm355 */
int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel);
/* enable/disable a vpss clock, 0 - success, -1 - failure */
int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en);
+/*set sync polarity, only implemented for DM365*/
+void vpss_set_sync_pol(struct vpss_sync_pol);
+/*set the PG_FRAME_SIZE register, only implemented for DM365*/
+void vpss_set_pg_frame_size(struct vpss_pg_frame_size);
/* wbl reset for dm644x */
enum vpss_wbl_sel {
--
1.6.0.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v1 3/4] CCDC support on DM365
2009-08-17 20:05 ` [PATCH v1 2/4] DM365 VPSS support neilsikka
@ 2009-08-17 20:05 ` neilsikka
2009-08-17 20:05 ` [PATCH v1 4/4] Build system support for DM365 CCDC neilsikka
0 siblings, 1 reply; 8+ messages in thread
From: neilsikka @ 2009-08-17 20:05 UTC (permalink / raw)
To: linux-media, davinci-linux-open-source; +Cc: khilman, hverkuil, Neil Sikka
From: Neil Sikka <neilsikka@ti.com>
This patch adds ccdc capture support for DM365 device.
This patch depends on Muralidharan's patches:
[PATCH] v4l: DaVinci: DM646x: Update the structure name as per header file
changes
[PATCH] V4L: ccdc driver - adding support for camera capture
[PATCH] V4L: ccdc driver - select MSP driver for CCDC input selection
[PATCH] V4L: vpfe capture driver - adding support for camera capture
Reviewed-by: Muralidharan Karicheri <m-karicheri2@ti.com>
Mandatory-Reviewer: Hans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: Neil Sikka <neilsikka@ti.com>
---
Applies to v4l-dvb linux-next repository
drivers/media/video/davinci/dm365_ccdc.c | 1410 +++++++++++++++++++++++++
drivers/media/video/davinci/dm365_ccdc_regs.h | 293 +++++
include/media/davinci/dm365_ccdc.h | 722 +++++++++++++
3 files changed, 2425 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/video/davinci/dm365_ccdc.c
create mode 100644 drivers/media/video/davinci/dm365_ccdc_regs.h
create mode 100644 include/media/davinci/dm365_ccdc.h
diff --git a/drivers/media/video/davinci/dm365_ccdc.c b/drivers/media/video/davinci/dm365_ccdc.c
new file mode 100644
index 0000000..d75960c
--- /dev/null
+++ b/drivers/media/video/davinci/dm365_ccdc.c
@@ -0,0 +1,1410 @@
+/*
+ * Copyright (C) 2008-2009 Texas Instruments Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This is the isif hardware module for DM365.
+ * TODO: 1) Raw bayer parameter settings and bayer capture
+ * 2) Add support for control ioctl
+ * 3) Add support for linearization
+ * 4) Test VPFE_CMD_S_CCDC_RAW_RARAMS ioctl
+ */
+#include <linux/delay.h>
+#include <mach/mux.h>
+#include <linux/device.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <linux/videodev2.h>
+#include <media/davinci/dm365_ccdc.h>
+#include <media/davinci/vpss.h>
+#include "dm365_ccdc_regs.h"
+#include "ccdc_hw_device.h"
+
+static struct device *dev;
+
+/* holds live module configuation paramaters */
+static struct ccdc_params_raw ccdc_hw_params_bayer = {
+ .pix_fmt = CCDC_PIXFMT_RAW,
+ .frm_fmt = CCDC_FRMFMT_PROGRESSIVE,
+ .win = CCDC_WIN_VGA,
+ .fid_pol = VPFE_PINPOL_POSITIVE,
+ .vd_pol = VPFE_PINPOL_POSITIVE,
+ .hd_pol = VPFE_PINPOL_POSITIVE,
+ .gain = {
+ .r_ye = {1, 0},
+ .gr_cy = {1, 0},
+ .gb_g = {1, 0},
+ .b_mg = {1, 0},
+ },
+ .cfa_pat = CCDC_CFA_PAT_MOSAIC,
+ .data_msb = CCDC_BIT_MSB_11,
+ .config_params = {
+ .data_size = CCDC_12_BITS,
+ .data_shift = CCDC_NO_SHIFT,
+ .col_pat_field0 = {
+ .olop = CCDC_GREEN_BLUE,
+ .olep = CCDC_BLUE,
+ .elop = CCDC_RED,
+ .elep = CCDC_GREEN_RED
+ },
+ .col_pat_field1 = {
+ .olop = CCDC_GREEN_BLUE,
+ .olep = CCDC_BLUE,
+ .elop = CCDC_RED,
+ .elep = CCDC_GREEN_RED
+ },
+ .test_pat_gen = 0
+ }
+};
+
+static struct ccdc_ycbcr_config ccdc_hw_params_ycbcr = {
+ .pix_fmt = CCDC_PIXFMT_YCBCR_8BIT,
+ .frm_fmt = CCDC_FRMFMT_INTERLACED,
+ .win = CCDC_WIN_NTSC,
+ .fid_pol = VPFE_PINPOL_POSITIVE,
+ .vd_pol = VPFE_PINPOL_POSITIVE,
+ .hd_pol = VPFE_PINPOL_POSITIVE,
+ .pix_order = CCDC_PIXORDER_CBYCRY,
+ .buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED
+};
+
+static enum ccdc_data_pack data_pack = CCDC_DATA_PACK8;
+
+/* Defauts for module configuation paramaters */
+static struct ccdc_config_params_raw ccdc_config_defaults = {
+ .linearize = {
+ .en = 0,
+ .corr_shft = CCDC_NO_SHIFT,
+ .scale_fact = {1, 0},
+ },
+ .df_csc = {
+ .df_or_csc = 0,
+ .csc = {
+ .en = 0
+ },
+ },
+ .dfc = {
+ .en = 0
+ },
+ .bclamp = {
+ .en = 0
+ },
+ .gain_offset = {
+ .gain = {
+ .r_ye = {1, 0},
+ .gr_cy = {1, 0},
+ .gb_g = {1, 0},
+ .b_mg = {1, 0},
+ },
+ },
+ .culling = {
+ .hcpat_odd = 0xff,
+ .hcpat_even = 0xff,
+ .vcpat = 0xff
+ },
+ .compress = {
+ .alg = CCDC_ALAW,
+ },
+};
+
+
+static enum vpfe_hw_if_type ccdc_if_type;
+static void *__iomem isif_base_addr;
+static int isif_addr_size;
+
+/* Raw Bayer formats */
+static u32 ccdc_raw_bayer_pix_formats[] =
+ {V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16};
+
+/* Raw YUV formats */
+static u32 ccdc_raw_yuv_pix_formats[] =
+ {V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV};
+
+/* register access routines */
+static inline u32 regr(u32 offset)
+{
+ return __raw_readl(isif_base_addr + offset);
+}
+
+static inline void regw(u32 val, u32 offset)
+{
+ __raw_writel(val, isif_base_addr + offset);
+}
+
+static void ccdc_enable(int en)
+{
+ unsigned int temp;
+
+ temp = regr(SYNCEN);
+ temp &= (~CCDC_SYNCEN_VDHDEN_MASK);
+ temp |= (en & CCDC_SYNCEN_VDHDEN_MASK);
+ regw(temp, SYNCEN);
+}
+
+static void ccdc_disable_all_modules(void)
+{
+ /* disable BC */
+ regw(0, CLAMPCFG);
+ /* disable vdfc */
+ regw(0, DFCCTL);
+ /* disable CSC */
+ regw(0, CSCCTL);
+ /* disable linearization */
+ regw(0, LINCFG0);
+ /* disable other modules here as they are supported */
+}
+
+static void ccdc_set_ccdc_base(void *addr, int size)
+{
+ isif_base_addr = addr;
+ isif_addr_size = size;
+}
+
+static void ccdc_enable_output_to_sdram(int en)
+{
+ unsigned int temp;
+
+ temp = regr(SYNCEN);
+ temp &= (~(CCDC_SYNCEN_WEN_MASK));
+ temp |= ((en << CCDC_SYNCEN_WEN_SHIFT) & CCDC_SYNCEN_WEN_MASK);
+ regw(temp, SYNCEN);
+}
+
+static void ccdc_config_culling(struct ccdc_cul *cul)
+{
+ u32 val;
+
+ /* Horizontal pattern */
+ val = (cul->hcpat_even) << CULL_PAT_EVEN_LINE_SHIFT;
+ val |= cul->hcpat_odd;
+ regw(val, CULH);
+
+ /* vertical pattern */
+ regw(cul->vcpat, CULV);
+
+ /* LPF */
+ ccdc_enable(cul->en_lpf << CCDC_LPF_SHIFT);
+}
+
+static void ccdc_config_gain_offset(void)
+{
+ struct ccdc_gain_offsets_adj *gain_off_ptr =
+ &ccdc_hw_params_bayer.config_params.gain_offset;
+ u32 val;
+
+ val = ((gain_off_ptr->gain_sdram_en & 1) << GAIN_SDRAM_EN_SHIFT) |
+ ((gain_off_ptr->gain_ipipe_en & 1) << GAIN_IPIPE_EN_SHIFT) |
+ ((gain_off_ptr->gain_h3a_en & 1) << GAIN_H3A_EN_SHIFT) |
+ ((gain_off_ptr->offset_sdram_en & 1) << OFST_SDRAM_EN_SHIFT) |
+ ((gain_off_ptr->offset_ipipe_en & 1) << OFST_IPIPE_EN_SHIFT) |
+ ((gain_off_ptr->offset_h3a_en & 1) << OFST_H3A_EN_SHIFT);
+
+ ccdc_enable(val);
+
+ val = ((
+ gain_off_ptr->gain.r_ye.integer & GAIN_INTEGER_MASK)
+ << GAIN_INTEGER_SHIFT);
+ val |= (ccdc_hw_params_bayer.
+ config_params.gain_offset.gain.r_ye.decimal &
+ GAIN_DECIMAL_MASK);
+ regw(val, CRGAIN);
+
+ val = ((gain_off_ptr->gain.gr_cy
+ .integer & GAIN_INTEGER_MASK) << GAIN_INTEGER_SHIFT);
+ val |= (gain_off_ptr->gain.gr_cy
+ .decimal & GAIN_DECIMAL_MASK);
+ regw(val, CGRGAIN);
+
+ val = ((gain_off_ptr->gain.gb_g
+ .integer & GAIN_INTEGER_MASK) << GAIN_INTEGER_SHIFT);
+ val |= (gain_off_ptr->gain.gb_g
+ .decimal & GAIN_DECIMAL_MASK);
+ regw(val, CGBGAIN);
+
+ val = ((gain_off_ptr->gain.b_mg
+ .integer & GAIN_INTEGER_MASK) << GAIN_INTEGER_SHIFT);
+ val |= (gain_off_ptr->gain.b_mg
+ .decimal & GAIN_DECIMAL_MASK);
+ regw(val, CBGAIN);
+
+ regw((gain_off_ptr->offset &
+ OFFSET_MASK), COFSTA);
+}
+
+static void ccdc_restore_defaults(void)
+{
+ enum vpss_ccdc_source_sel source = VPSS_CCDCIN;
+ int i;
+
+ memcpy(&ccdc_hw_params_bayer.config_params, &ccdc_config_defaults,
+ sizeof(struct ccdc_config_params_raw));
+
+ /* disable CCDC */
+ dev_dbg(dev, "\nstarting ccdc_restore_defaults...");
+ /* Enable clock to ISIF, IPIPEIF and BL */
+ vpss_enable_clock(VPSS_CCDC_CLOCK, 1);
+ vpss_enable_clock(VPSS_IPIPEIF_CLOCK, 1);
+ vpss_enable_clock(VPSS_BL_CLOCK, 1);
+
+ /* set all registers to default value */
+ for (i = 0; i <= 0x1f8; i += 4)
+ regw(0, i);
+
+ /* no culling support */
+ regw(0xffff, CULH);
+ regw(0xff, CULV);
+
+ /* Set default offset and gain */
+ ccdc_config_gain_offset();
+
+ vpss_select_ccdc_source(source);
+
+ dev_dbg(dev, "\nEnd of ccdc_restore_defaults...");
+}
+
+static int ccdc_open(struct device *device)
+{
+ dev = device;
+ ccdc_restore_defaults();
+
+ return 0;
+}
+
+/* This function will configure the window size to be capture in CCDC reg */
+static void ccdc_setwin(struct v4l2_rect *image_win,
+ enum ccdc_frmfmt frm_fmt, int ppc)
+{
+ int horz_start, horz_nr_pixels;
+ int vert_start, vert_nr_lines;
+ int mid_img = 0;
+
+ dev_dbg(dev, "\nStarting ccdc_setwin...");
+ /**
+ * ppc - per pixel count. indicates how many pixels per cell
+ * output to SDRAM. example, for ycbcr, it is one y and one c, so 2.
+ * raw capture this is 1
+ */
+ horz_start = image_win->left << (ppc - 1);
+ horz_nr_pixels = ((image_win->width) << (ppc - 1)) - 1;
+
+ /* Writing the horizontal info into the registers */
+ regw(horz_start & START_PX_HOR_MASK, SPH);
+ regw(horz_nr_pixels & NUM_PX_HOR_MASK, LNH);
+ vert_start = image_win->top;
+
+ if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
+ vert_nr_lines = (image_win->height >> 1) - 1;
+ vert_start >>= 1;
+ /* To account for VD since line 0 doesn't have any data */
+ vert_start += 1;
+ } else {
+ /* To account for VD since line 0 doesn't have any data */
+ vert_start += 1;
+ vert_nr_lines = image_win->height - 1;
+ /* configure VDINT0 and VDINT1 */
+ mid_img = vert_start + (image_win->height / 2);
+ regw(mid_img, VDINT1);
+ }
+
+ regw(0, VDINT0);
+ regw(vert_start & START_VER_ONE_MASK, SLV0);
+ regw(vert_start & START_VER_TWO_MASK, SLV1);
+ regw(vert_nr_lines & NUM_LINES_VER, LNV);
+}
+
+static void ccdc_config_bclamp(struct ccdc_black_clamp *bc)
+{
+ u32 val;
+
+ /**
+ * DC Offset is always added to image data irrespective of bc enable
+ * status
+ */
+ val = bc->dc_offset & CCDC_BC_DCOFFSET_MASK;
+ regw(val, CLDCOFST);
+
+ if (bc->en) {
+ val = (bc->bc_mode_color & CCDC_BC_MODE_COLOR_MASK) <<
+ CCDC_BC_MODE_COLOR_SHIFT;
+
+ /* Enable BC and horizontal clamp caculation paramaters */
+ val = val | 1 | ((bc->horz.mode & CCDC_HORZ_BC_MODE_MASK) <<
+ CCDC_HORZ_BC_MODE_SHIFT);
+
+ regw(val, CLAMPCFG);
+
+ if (bc->horz.mode != CCDC_HORZ_BC_DISABLE) {
+ /**
+ * Window count for calculation
+ * Base window selection
+ * pixel limit
+ * Horizontal size of window
+ * vertical size of the window
+ * Horizontal start position of the window
+ * Vertical start position of the window
+ */
+ val = (bc->horz.win_count_calc &
+ CCDC_HORZ_BC_WIN_COUNT_MASK) |
+ ((bc->horz.base_win_sel_calc & 1)
+ << CCDC_HORZ_BC_WIN_SEL_SHIFT) |
+ ((bc->horz.clamp_pix_limit & 1)
+ << CCDC_HORZ_BC_PIX_LIMIT_SHIFT) |
+ ((bc->horz.win_h_sz_calc &
+ CCDC_HORZ_BC_WIN_H_SIZE_MASK)
+ << CCDC_HORZ_BC_WIN_H_SIZE_SHIFT) |
+ ((bc->horz.win_v_sz_calc &
+ CCDC_HORZ_BC_WIN_V_SIZE_MASK)
+ << CCDC_HORZ_BC_WIN_V_SIZE_SHIFT);
+
+ regw(val, CLHWIN0);
+
+ val = (bc->horz.win_start_h_calc &
+ CCDC_HORZ_BC_WIN_START_H_MASK);
+ regw(val, CLHWIN1);
+
+ val =
+ (bc->horz.
+ win_start_v_calc & CCDC_HORZ_BC_WIN_START_V_MASK);
+ regw(val, CLHWIN2);
+ }
+
+ /* vertical clamp caculation paramaters */
+
+ /* OB H Valid */
+ val = (bc->vert.ob_h_sz_calc & CCDC_VERT_BC_OB_H_SZ_MASK);
+
+ /* Reset clamp value sel for previous line */
+ val |= ((bc->vert.reset_val_sel &
+ CCDC_VERT_BC_RST_VAL_SEL_MASK)
+ << CCDC_VERT_BC_RST_VAL_SEL_SHIFT);
+
+ /* Line average coefficient */
+ val |= (bc->vert.line_ave_coef <<
+ CCDC_VERT_BC_LINE_AVE_COEF_SHIFT);
+ regw(val, CLVWIN0);
+
+ /* Configured reset value */
+ if (bc->vert.reset_val_sel ==
+ CCDC_VERT_BC_USE_CONFIG_CLAMP_VAL) {
+ val =
+ (bc->vert.
+ reset_clamp_val & CCDC_VERT_BC_RST_VAL_MASK);
+ regw(val, CLVRV);
+ }
+
+ /* Optical Black horizontal start position */
+ val = (bc->vert.ob_start_h & CCDC_VERT_BC_OB_START_HORZ_MASK);
+ regw(val, CLVWIN1);
+
+ /* Optical Black vertical start position */
+ val = (bc->vert.ob_start_v & CCDC_VERT_BC_OB_START_VERT_MASK);
+ regw(val, CLVWIN2);
+
+ val = (bc->vert.ob_v_sz_calc & CCDC_VERT_BC_OB_VERT_SZ_MASK);
+ regw(val, CLVWIN3);
+
+ /* Vertical start position for BC subtraction */
+ val = (bc->vert_start_sub & CCDC_BC_VERT_START_SUB_V_MASK);
+ regw(val, CLSV);
+ }
+}
+
+static void ccdc_config_dfc(struct ccdc_dfc *vdfc)
+{
+#define DFC_WRITE_WAIT_COUNT 1000
+ u32 val, count = DFC_WRITE_WAIT_COUNT;
+ int i;
+
+ if (!vdfc->en)
+ return;
+
+ /* Correction mode */
+ val = ((vdfc->corr_mode & CCDC_VDFC_CORR_MOD_MASK)
+ << CCDC_VDFC_CORR_MOD_SHIFT);
+
+ /* Correct whole line or partial */
+ if (vdfc->corr_whole_line)
+ val |= 1 << CCDC_VDFC_CORR_WHOLE_LN_SHIFT;
+
+ /* level shift value */
+ val |= (vdfc->def_level_shift & CCDC_VDFC_LEVEL_SHFT_MASK) <<
+ CCDC_VDFC_LEVEL_SHFT_SHIFT;
+
+ regw(val, DFCCTL);
+
+ /* Defect saturation level */
+ val = vdfc->def_sat_level & CCDC_VDFC_SAT_LEVEL_MASK;
+ regw(val, VDFSATLV);
+
+ regw(vdfc->table[0].pos_vert & CCDC_VDFC_POS_MASK, DFCMEM0);
+ regw(vdfc->table[0].pos_horz & CCDC_VDFC_POS_MASK, DFCMEM1);
+ if (vdfc->corr_mode == CCDC_VDFC_NORMAL ||
+ vdfc->corr_mode == CCDC_VDFC_HORZ_INTERPOL_IF_SAT) {
+ regw(vdfc->table[0].level_at_pos, DFCMEM2);
+ regw(vdfc->table[0].level_up_pixels, DFCMEM3);
+ regw(vdfc->table[0].level_low_pixels, DFCMEM4);
+ }
+
+ val = regr(DFCMEMCTL);
+ /* set DFCMARST and set DFCMWR */
+ val |= 1 << CCDC_DFCMEMCTL_DFCMARST_SHIFT;
+ val |= 1;
+ regw(val, DFCMEMCTL);
+
+ while (count && (regr(DFCMEMCTL) & 0x01))
+ count--;
+
+ val = regr(DFCMEMCTL);
+ if (!count) {
+ dev_err(dev, "defect table write timeout !!!\n");
+ return;
+ }
+
+ for (i = 1; i < vdfc->num_vdefects; i++) {
+ regw(vdfc->table[i].pos_vert & CCDC_VDFC_POS_MASK,
+ DFCMEM0);
+ regw(vdfc->table[i].pos_horz & CCDC_VDFC_POS_MASK,
+ DFCMEM1);
+ if (vdfc->corr_mode == CCDC_VDFC_NORMAL ||
+ vdfc->corr_mode == CCDC_VDFC_HORZ_INTERPOL_IF_SAT) {
+ regw(vdfc->table[i].level_at_pos, DFCMEM2);
+ regw(vdfc->table[i].level_up_pixels, DFCMEM3);
+ regw(vdfc->table[i].level_low_pixels, DFCMEM4);
+ }
+ val = regr(DFCMEMCTL);
+ /* clear DFCMARST and set DFCMWR */
+ val &= ~(1 << CCDC_DFCMEMCTL_DFCMARST_SHIFT);
+ val |= 1;
+ regw(val, DFCMEMCTL);
+
+ count = DFC_WRITE_WAIT_COUNT;
+ while (count && (regr(DFCMEMCTL) & 0x01))
+ count--;
+
+ val = regr(DFCMEMCTL);
+ if (!count) {
+ dev_err(dev, "defect table write timeout !!!\n");
+ return;
+ }
+ }
+ if (vdfc->num_vdefects < CCDC_VDFC_TABLE_SIZE) {
+ /* Extra cycle needed */
+ regw(0, DFCMEM0);
+ regw(0x1FFF, DFCMEM1);
+ val = 1;
+ regw(val, DFCMEMCTL);
+ }
+
+ /* enable VDFC */
+ ccdc_enable((1 << CCDC_VDFC_EN_SHIFT));
+
+ ccdc_enable((0 << CCDC_VDFC_EN_SHIFT));
+
+ regw(0x6, DFCMEMCTL);
+ for (i = 0 ; i < vdfc->num_vdefects; i++) {
+ count = DFC_WRITE_WAIT_COUNT;
+ while (count && (regr(DFCMEMCTL) & 0x2))
+ count--;
+
+ val = regr(DFCMEMCTL);
+ if (!count) {
+ dev_err(dev, "defect table write timeout !!!\n");
+ return;
+ }
+
+ val = regr(DFCMEM0) | regr(DFCMEM1) | regr(DFCMEM2) |
+ regr(DFCMEM3) | regr(DFCMEM4);
+ regw(0x2, DFCMEMCTL);
+ }
+}
+
+static void ccdc_config_csc(struct ccdc_df_csc *df_csc)
+{
+ u32 val1 = 0, val2 = 0, i;
+
+ if (!df_csc->csc.en) {
+ regw(0, CSCCTL);
+ return;
+ }
+ for (i = 0; i < CCDC_CSC_NUM_COEFF; i++) {
+ if ((i % 2) == 0) {
+ /* CSCM - LSB */
+ val1 =
+ ((df_csc->csc.coeff[i].integer &
+ CCDC_CSC_COEF_INTEG_MASK)
+ << CCDC_CSC_COEF_INTEG_SHIFT) |
+ ((df_csc->csc.coeff[i].decimal &
+ CCDC_CSC_COEF_DECIMAL_MASK));
+ } else {
+
+ /* CSCM - MSB */
+ val2 =
+ ((df_csc->csc.coeff[i].integer &
+ CCDC_CSC_COEF_INTEG_MASK)
+ << CCDC_CSC_COEF_INTEG_SHIFT) |
+ ((df_csc->csc.coeff[i].decimal &
+ CCDC_CSC_COEF_DECIMAL_MASK));
+ val2 <<= CCDC_CSCM_MSB_SHIFT;
+ val2 |= val1;
+ regw(val2, (CSCM0 + ((i-1) << 1)));
+ }
+ }
+
+ /* program the active area */
+ regw(df_csc->start_pix & CCDC_DF_CSC_SPH_MASK, FMTSPH);
+ /**
+ * one extra pixel as required for CSC. Actually number of
+ * pixel - 1 should be configured in this register. So we
+ * need to subtract 1 before writing to FMTSPH, but we will
+ * not do this since csc requires one extra pixel
+ */
+ regw((df_csc->num_pixels) & CCDC_DF_CSC_SPH_MASK, FMTLNH);
+ regw(df_csc->start_line & CCDC_DF_CSC_SPH_MASK, FMTSLV);
+ /**
+ * one extra line as required for CSC. See reason documented for
+ * num_pixels
+ */
+ regw((df_csc->num_lines) & CCDC_DF_CSC_SPH_MASK, FMTLNV);
+
+ /* Enable CSC */
+ regw(1, CSCCTL);
+}
+
+static int ccdc_config_raw(int mode)
+{
+ struct ccdc_params_raw *params = &ccdc_hw_params_bayer;
+ struct ccdc_config_params_raw *module_params =
+ &ccdc_hw_params_bayer.config_params;
+ struct vpss_pg_frame_size frame_size;
+ struct vpss_sync_pol sync;
+ u32 val;
+
+ dev_dbg(dev, "\nStarting ccdc_config_raw..\n");
+ ccdc_restore_defaults();
+
+ /* Configure CCDCFG register */
+
+ /**
+ *Set CCD Not to swap input since input is RAW data
+ *set FID detection function to Latch at V-Sync
+ *set WENLOG - ccdc valid area
+ *set TRGSEL
+ *set EXTRG
+ * Packed to 8 or 16 bits
+ */
+
+ val = CCDC_YCINSWP_RAW | CCDC_CCDCFG_FIDMD_LATCH_VSYNC |
+ CCDC_CCDCFG_WENLOG_AND | CCDC_CCDCFG_TRGSEL_WEN |
+ CCDC_CCDCFG_EXTRG_DISABLE | (data_pack & CCDC_DATA_PACK_MASK);
+
+ dev_dbg(dev, "Writing 0x%x to ...CCDCFG \n", val);
+ regw(val, CCDCFG);
+
+ /**
+ * Configure the vertical sync polarity(MODESET.VDPOL)
+ * Configure the horizontal sync polarity (MODESET.HDPOL)
+ * Configure frame id polarity (MODESET.FLDPOL)
+ * Configure data polarity
+ * Configure External WEN Selection
+ * Configure frame format(progressive or interlace)
+ * Configure pixel format (Input mode)
+ * Configure the data shift
+ */
+
+ val = CCDC_VDHDOUT_INPUT |
+ ((params->vd_pol & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT) |
+ ((params->hd_pol & CCDC_HD_POL_MASK) << CCDC_HD_POL_SHIFT) |
+ ((params->fid_pol & CCDC_FID_POL_MASK) << CCDC_FID_POL_SHIFT) |
+ ((CCDC_DATAPOL_NORMAL & CCDC_DATAPOL_MASK)
+ << CCDC_DATAPOL_SHIFT) |
+ ((CCDC_EXWEN_DISABLE & CCDC_EXWEN_MASK) << CCDC_EXWEN_SHIFT) |
+ ((params->frm_fmt & CCDC_FRM_FMT_MASK) << CCDC_FRM_FMT_SHIFT) |
+ ((params->pix_fmt & CCDC_INPUT_MASK) << CCDC_INPUT_SHIFT) |
+ ((params->config_params.data_shift & CCDC_DATASFT_MASK)
+ << CCDC_DATASFT_SHIFT);
+
+ regw(val, MODESET);
+ dev_dbg(dev, "Writing 0x%x to MODESET...\n", val);
+
+ /**
+ * Configure GAMMAWD register
+ * CFA pattern setting
+ */
+ val = (params->cfa_pat & CCDC_GAMMAWD_CFA_MASK) <<
+ CCDC_GAMMAWD_CFA_SHIFT;
+
+ /* Gamma msb */
+ if (module_params->compress.alg == CCDC_ALAW) {
+ val = val | CCDC_ALAW_ENABLE |
+ ((params->data_msb & CCDC_ALAW_GAMA_WD_MASK) <<
+ CCDC_ALAW_GAMA_WD_SHIFT);
+ }
+
+ regw(val, CGAMMAWD);
+
+ /* Configure DPCM compression settings */
+ if (module_params->compress.alg == CCDC_DPCM) {
+ val = 1 << CCDC_DPCM_EN_SHIFT;
+ val |= (module_params->compress.pred &
+ CCDC_DPCM_PREDICTOR_MASK) << CCDC_DPCM_PREDICTOR_SHIFT;
+ }
+
+ regw(val, MISC);
+ /* Configure Gain & Offset */
+
+ ccdc_config_gain_offset();
+
+ /* Configure Color pattern */
+ val = (params->config_params.col_pat_field0.olop) |
+ (params->config_params.col_pat_field0.olep << 2) |
+ (params->config_params.col_pat_field0.elop << 4) |
+ (params->config_params.col_pat_field0.elep << 6) |
+ (params->config_params.col_pat_field1.olop << 8) |
+ (params->config_params.col_pat_field1.olep << 10) |
+ (params->config_params.col_pat_field1.elop << 12) |
+ (params->config_params.col_pat_field1.elep << 14);
+ regw(val, CCOLP);
+ dev_dbg(dev, "Writing %x to CCOLP ...\n", val);
+
+ /* Configure HSIZE register */
+ val =
+ (params->
+ horz_flip_en & CCDC_HSIZE_FLIP_MASK) << CCDC_HSIZE_FLIP_SHIFT;
+
+ /* calculate line offset in 32 bytes based on pack value */
+ if (data_pack == CCDC_PACK_8BIT)
+ val |= (((params->win.width + 31) >> 5) & CCDC_LINEOFST_MASK);
+ else if (data_pack == CCDC_PACK_12BIT)
+ val |= ((((params->win.width +
+ (params->win.width >> 2)) +
+ 31) >> 5) & CCDC_LINEOFST_MASK);
+ else
+ val |=
+ ((((params->win.width * 2) +
+ 31) >> 5) & CCDC_LINEOFST_MASK);
+ regw(val, HSIZE);
+
+ /* Configure SDOFST register */
+ if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) {
+ if (params->image_invert_en) {
+ /* For interlace inverse mode */
+ regw(0x4B6D, SDOFST);
+ dev_dbg(dev, "Writing 0x4B6D to SDOFST...\n");
+ } else {
+ /* For interlace non inverse mode */
+ regw(0x0B6D, SDOFST);
+ dev_dbg(dev, "Writing 0x0B6D to SDOFST...\n");
+ }
+ } else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) {
+ if (params->image_invert_en) {
+ /* For progessive inverse mode */
+ regw(0x4000, SDOFST);
+ dev_dbg(dev, "Writing 0x4000 to SDOFST...\n");
+ } else {
+ /* For progessive non inverse mode */
+ regw(0x0000, SDOFST);
+ dev_dbg(dev, "Writing 0x0000 to SDOFST...\n");
+ }
+ }
+
+ /* Configure video window */
+ ccdc_setwin(¶ms->win, params->frm_fmt, 1);
+
+ /* Configure Black Clamp */
+ ccdc_config_bclamp(&module_params->bclamp);
+
+ /* Configure Vertical Defection Pixel Correction */
+ ccdc_config_dfc(&module_params->dfc);
+
+ if (!module_params->df_csc.df_or_csc) {
+ /* Configure Color Space Conversion */
+ ccdc_config_csc(&module_params->df_csc);
+ }
+
+ /* Configure Culling */
+ ccdc_config_culling(&module_params->culling);
+
+ /* Configure Horizontal and vertical offsets(DFC,LSC,Gain) */
+ val = module_params->horz_offset & CCDC_DATA_H_OFFSET_MASK;
+ regw(val, DATAHOFST);
+
+ val = module_params->vert_offset & CCDC_DATA_V_OFFSET_MASK;
+ regw(val, DATAVOFST);
+
+ /* Setup test pattern if enabled */
+ if (params->config_params.test_pat_gen) {
+ /* configure pattern register */
+
+ /* Use the HD/VD pol settings from user */
+ sync.ccdpg_hdpol = params->hd_pol & CCDC_HD_POL_MASK;
+ sync.ccdpg_vdpol = params->vd_pol & CCDC_VD_POL_MASK;
+
+ vpss_set_sync_pol(sync);
+
+ frame_size.hlpfr = ccdc_hw_params_bayer.win.width;
+ frame_size.pplen = ccdc_hw_params_bayer.win.height;
+ vpss_set_pg_frame_size(frame_size);
+ vpss_select_ccdc_source(VPSS_PGLPBK);
+ } else
+ dev_dbg(dev, "\nEnd of ccdc_config_ycbcr...\n");
+
+ return 0;
+}
+
+static int ccdc_validate_df_csc_params(struct ccdc_df_csc *df_csc)
+{
+ struct ccdc_color_space_conv *csc;
+ int i, csc_df_en = 0;
+ int err = -EINVAL;
+
+ if (!df_csc->df_or_csc) {
+ /* csc configuration */
+ csc = &df_csc->csc;
+ if (csc->en) {
+ csc_df_en = 1;
+ for (i = 0; i < CCDC_CSC_NUM_COEFF; i++) {
+ if (csc->coeff[i].integer >
+ CCDC_CSC_COEF_INTEG_MASK ||
+ csc->coeff[i].decimal >
+ CCDC_CSC_COEF_DECIMAL_MASK) {
+ printk(KERN_ERR
+ "invalid csc coefficients \n");
+ return err;
+ }
+ }
+ }
+ }
+
+ if (df_csc->start_pix > CCDC_DF_CSC_SPH_MASK) {
+ dev_err(dev, "invalid df_csc start pix value \n");
+ return err;
+ }
+ if (df_csc->num_pixels > CCDC_DF_NUMPIX) {
+ dev_err(dev, "invalid df_csc num pixels value \n");
+ return err;
+ }
+ if (df_csc->start_line > CCDC_DF_CSC_LNH_MASK) {
+ dev_err(dev, "invalid df_csc start_line value \n");
+ return err;
+ }
+ if (df_csc->num_lines > CCDC_DF_NUMLINES) {
+ dev_err(dev, "invalid df_csc num_lines value \n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int ccdc_validate_dfc_params(struct ccdc_dfc *dfc)
+{
+ int err = -EINVAL;
+ int i;
+
+ if (dfc->en) {
+ if (dfc->corr_whole_line > 1) {
+ dev_err(dev, "invalid corr_whole_line value \n");
+ return err;
+ }
+
+ if (dfc->def_level_shift > 4) {
+ dev_err(dev, "invalid def_level_shift value \n");
+ return err;
+ }
+
+ if (dfc->def_sat_level > 4095) {
+ dev_err(dev, "invalid def_sat_level value \n");
+ return err;
+ }
+ if ((!dfc->num_vdefects) || (dfc->num_vdefects > 8)) {
+ dev_err(dev, "invalid num_vdefects value \n");
+ return err;
+ }
+ for (i = 0; i < CCDC_VDFC_TABLE_SIZE; i++) {
+ if (dfc->table[i].pos_vert > 0x1fff) {
+ dev_err(dev, "invalid pos_vert value \n");
+ return err;
+ }
+ if (dfc->table[i].pos_horz > 0x1fff) {
+ dev_err(dev, "invalid pos_horz value \n");
+ return err;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int ccdc_validate_bclamp_params(struct ccdc_black_clamp *bclamp)
+{
+ int err = -EINVAL;
+
+ if (bclamp->dc_offset > 0x1fff) {
+ dev_err(dev, "invalid bclamp dc_offset value \n");
+ return err;
+ }
+
+ if (bclamp->en) {
+ if (bclamp->horz.clamp_pix_limit > 1) {
+ printk(KERN_ERR
+ "invalid bclamp horz clamp_pix_limit value \n");
+ return err;
+ }
+
+ if (bclamp->horz.win_count_calc < 1 ||
+ bclamp->horz.win_count_calc > 32) {
+ printk(KERN_ERR
+ "invalid bclamp horz win_count_calc value \n");
+ return err;
+ }
+
+ if (bclamp->horz.win_start_h_calc > 0x1fff) {
+ printk(KERN_ERR
+ "invalid bclamp win_start_v_calc value \n");
+ return err;
+ }
+
+ if (bclamp->horz.win_start_v_calc > 0x1fff) {
+ printk(KERN_ERR
+ "invalid bclamp win_start_v_calc value \n");
+ return err;
+ }
+
+ if (bclamp->vert.reset_clamp_val > 0xfff) {
+ printk(KERN_ERR
+ "invalid bclamp reset_clamp_val value \n");
+ return err;
+ }
+
+ if (bclamp->vert.ob_v_sz_calc > 0x1fff) {
+ dev_err(dev, "invalid bclamp ob_v_sz_calc value \n");
+ return err;
+ }
+
+ if (bclamp->vert.ob_start_h > 0x1fff) {
+ dev_err(dev, "invalid bclamp ob_start_h value \n");
+ return err;
+ }
+
+ if (bclamp->vert.ob_start_v > 0x1fff) {
+ dev_err(dev, "invalid bclamp ob_start_h value \n");
+ return err;
+ }
+ }
+
+ return 0;
+}
+
+static int ccdc_validate_gain_ofst_params(struct ccdc_gain_offsets_adj
+ *gain_offset)
+{
+ int err = -EINVAL;
+
+ if (gain_offset->gain_sdram_en ||
+ gain_offset->gain_ipipe_en ||
+ gain_offset->gain_h3a_en) {
+ if ((gain_offset->gain.r_ye.integer > 7) ||
+ (gain_offset->gain.r_ye.decimal > 0x1ff)) {
+ dev_err(dev, "invalid gain r_ye\n");
+ return err;
+ }
+ if ((gain_offset->gain.gr_cy.integer > 7) ||
+ (gain_offset->gain.gr_cy.decimal > 0x1ff)) {
+ dev_err(dev, "invalid gain gr_cy\n");
+ return err;
+ }
+ if ((gain_offset->gain.gb_g.integer > 7) ||
+ (gain_offset->gain.gb_g.decimal > 0x1ff)) {
+ dev_err(dev, "invalid gain gb_g\n");
+ return err;
+ }
+ if ((gain_offset->gain.b_mg.integer > 7) ||
+ (gain_offset->gain.b_mg.decimal > 0x1ff)) {
+ dev_err(dev, "invalid gain b_mg\n");
+ return err;
+ }
+ }
+ if (gain_offset->offset_sdram_en ||
+ gain_offset->offset_ipipe_en ||
+ gain_offset->offset_h3a_en) {
+ if (gain_offset->offset > 0xfff) {
+ dev_err(dev, "invalid gain b_mg\n");
+ return err;
+ }
+ }
+
+ return 0;
+}
+
+static int validate_ccdc_config_params_raw(struct ccdc_params_raw *param)
+{
+ struct ccdc_config_params_raw *module_params;
+ int err = 0;
+
+ if ((param == NULL) || (¶m->config_params == NULL)) {
+ printk(KERN_ERR
+ "Invalid argument for validate_ccdc_config_params_raw()\n");
+ return err;
+ }
+ module_params = kmalloc(sizeof(struct ccdc_config_params_raw),
+ GFP_KERNEL);
+ if (module_params == NULL) {
+ dev_err(dev, "memory allocation failure\n");
+ return -EFAULT;
+ }
+ if (copy_from_user(module_params, ¶m->config_params,
+ sizeof(struct ccdc_config_params_raw))) {
+ printk(KERN_ERR
+ "error in copying ccdc params to kernel\n");
+ kfree(module_params);
+ return -EFAULT;
+ }
+ err = ccdc_validate_df_csc_params(&module_params->df_csc);
+ if (err)
+ goto free_exit;
+ err |= ccdc_validate_dfc_params(&module_params->dfc);
+ if (err)
+ goto free_exit;
+ err |= ccdc_validate_bclamp_params(&module_params->bclamp);
+ if (err)
+ goto free_exit;
+ err |= ccdc_validate_gain_ofst_params(&module_params->gain_offset);
+ if (err)
+ goto free_exit;
+ memcpy(&ccdc_hw_params_bayer.config_params, module_params,
+ sizeof(struct ccdc_config_params_raw));
+
+free_exit:
+ kfree(module_params);
+ return err;
+}
+
+static int ccdc_set_buftype(enum ccdc_buftype buf_type)
+{
+ if (ccdc_if_type == VPFE_RAW_BAYER)
+ ccdc_hw_params_bayer.buf_type = buf_type;
+ else
+ ccdc_hw_params_ycbcr.buf_type = buf_type;
+
+ return 0;
+
+}
+static enum ccdc_buftype ccdc_get_buftype(void)
+{
+ if (ccdc_if_type == VPFE_RAW_BAYER)
+ return ccdc_hw_params_bayer.buf_type;
+
+ return ccdc_hw_params_ycbcr.buf_type;
+}
+
+static int ccdc_enum_pix(u32 *pix, int i)
+{
+ int ret = -EINVAL;
+
+ if (ccdc_if_type == VPFE_RAW_BAYER) {
+ if (i < ARRAY_SIZE(ccdc_raw_bayer_pix_formats)) {
+ *pix = ccdc_raw_bayer_pix_formats[i];
+ ret = 0;
+ }
+ } else {
+ if (i < ARRAY_SIZE(ccdc_raw_yuv_pix_formats)) {
+ *pix = ccdc_raw_yuv_pix_formats[i];
+ ret = 0;
+ }
+ }
+
+ return ret;
+}
+
+static int ccdc_set_pixel_format(unsigned int pixfmt)
+{
+ if (ccdc_if_type == VPFE_RAW_BAYER) {
+ if (pixfmt == V4L2_PIX_FMT_SBGGR8) {
+ if ((ccdc_hw_params_bayer.config_params.compress.alg !=
+ CCDC_ALAW) &&
+ (ccdc_hw_params_bayer.config_params.compress.alg !=
+ CCDC_DPCM)) {
+ dev_err(dev, "Either configure A-Law or"
+ "DPCM\n");
+ return -EINVAL;
+ }
+ data_pack = CCDC_PACK_8BIT;
+ } else if (pixfmt == V4L2_PIX_FMT_SBGGR16) {
+ if (ccdc_hw_params_bayer.config_params.compress.alg !=
+ CCDC_NO_COMPRESSION) {
+ dev_err(dev, "Disable compression"
+ " for this pixel format\n");
+ return -EINVAL;
+ }
+ data_pack = CCDC_PACK_16BIT;
+ } else
+ return -EINVAL;
+ ccdc_hw_params_bayer.pix_fmt = CCDC_PIXFMT_RAW;
+ } else {
+ if (pixfmt == V4L2_PIX_FMT_YUYV)
+ ccdc_hw_params_ycbcr.pix_order = CCDC_PIXORDER_YCBYCR;
+ else if (pixfmt == V4L2_PIX_FMT_UYVY)
+ ccdc_hw_params_ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
+ else
+ return -EINVAL;
+ data_pack = CCDC_PACK_8BIT;
+ }
+
+ return 0;
+}
+
+static u32 ccdc_get_pixel_format(void)
+{
+ u32 pixfmt;
+
+ if (ccdc_if_type == VPFE_RAW_BAYER)
+ if (ccdc_hw_params_bayer.config_params.compress.alg
+ == CCDC_ALAW
+ || ccdc_hw_params_bayer.config_params.compress.alg
+ == CCDC_DPCM)
+ pixfmt = V4L2_PIX_FMT_SBGGR8;
+ else
+ pixfmt = V4L2_PIX_FMT_SBGGR16;
+ else {
+ if (ccdc_hw_params_ycbcr.pix_order == CCDC_PIXORDER_YCBYCR)
+ pixfmt = V4L2_PIX_FMT_YUYV;
+ else
+ pixfmt = V4L2_PIX_FMT_UYVY;
+ }
+
+ return pixfmt;
+}
+
+static int ccdc_set_image_window(struct v4l2_rect *win)
+{
+ if (ccdc_if_type == VPFE_RAW_BAYER) {
+ ccdc_hw_params_bayer.win.top = win->top;
+ ccdc_hw_params_bayer.win.left = win->left;
+ ccdc_hw_params_bayer.win.width = win->width;
+ ccdc_hw_params_bayer.win.height = win->height;
+ } else {
+ ccdc_hw_params_ycbcr.win.top = win->top;
+ ccdc_hw_params_ycbcr.win.left = win->left;
+ ccdc_hw_params_ycbcr.win.width = win->width;
+ ccdc_hw_params_ycbcr.win.height = win->height;
+ }
+
+ return 0;
+}
+
+static void ccdc_get_image_window(struct v4l2_rect *win)
+{
+ if (ccdc_if_type == VPFE_RAW_BAYER)
+ *win = ccdc_hw_params_bayer.win;
+ else
+ *win = ccdc_hw_params_ycbcr.win;
+}
+
+static unsigned int ccdc_get_line_length(void)
+{
+ unsigned int len;
+
+ if (ccdc_if_type == VPFE_RAW_BAYER) {
+ if (data_pack == CCDC_PACK_8BIT)
+ len = ((ccdc_hw_params_bayer.win.width));
+ else if (data_pack == CCDC_PACK_12BIT)
+ len = (((ccdc_hw_params_bayer.win.width * 2) +
+ (ccdc_hw_params_bayer.win.width >> 2)));
+ else
+ len = (((ccdc_hw_params_bayer.win.width * 2)));
+ } else
+ len = (((ccdc_hw_params_ycbcr.win.width * 2)));
+
+ return ALIGN(len, 32);
+}
+
+static int ccdc_set_frame_format(enum ccdc_frmfmt frm_fmt)
+{
+ if (ccdc_if_type == VPFE_RAW_BAYER)
+ ccdc_hw_params_bayer.frm_fmt = frm_fmt;
+ else
+ ccdc_hw_params_ycbcr.frm_fmt = frm_fmt;
+
+ return 0;
+}
+static enum ccdc_frmfmt ccdc_get_frame_format(void)
+{
+ if (ccdc_if_type == VPFE_RAW_BAYER)
+ return ccdc_hw_params_bayer.frm_fmt;
+ else
+ return ccdc_hw_params_ycbcr.frm_fmt;
+}
+
+static int ccdc_getfid(void)
+{
+ return (regr(MODESET) >> 15) & 0x1;
+}
+
+/* misc operations */
+static void ccdc_setfbaddr(unsigned long addr)
+{
+ regw((addr >> 21) & 0x07ff, CADU);
+ regw((addr >> 5) & 0x0ffff, CADL);
+}
+
+static int ccdc_set_hw_if_params(struct vpfe_hw_if_param *params)
+{
+ ccdc_if_type = params->if_type;
+
+ switch (params->if_type) {
+ case VPFE_BT656:
+ case VPFE_BT656_10BIT:
+ case VPFE_YCBCR_SYNC_8:
+ ccdc_hw_params_ycbcr.pix_fmt = CCDC_PIXFMT_YCBCR_8BIT;
+ ccdc_hw_params_ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
+ break;
+ case VPFE_BT1120:
+ case VPFE_YCBCR_SYNC_16:
+ ccdc_hw_params_ycbcr.pix_fmt = CCDC_PIXFMT_YCBCR_16BIT;
+ ccdc_hw_params_ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
+ break;
+ case VPFE_RAW_BAYER:
+ ccdc_hw_params_bayer.pix_fmt = CCDC_PIXFMT_RAW;
+ break;
+ default:
+ dev_err(dev, "Invalid interface type\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/* Parameter operations */
+static int ccdc_set_params(void __user *params)
+{
+ struct ccdc_params_raw ccdc_raw_params;
+ int ret;
+
+ /* only raw module parameters can be set through the IOCTL */
+ if (ccdc_if_type != VPFE_RAW_BAYER)
+ return -EINVAL;
+
+ ret = copy_from_user(&ccdc_raw_params, params, sizeof(ccdc_raw_params));
+ if (ret) {
+ dev_dbg(dev, "ccdc_set_params: error in copying ccdc"
+ "params, %d\n", ret);
+ return -EFAULT;
+ }
+
+ if (!validate_ccdc_config_params_raw(&ccdc_raw_params)) {
+ /**
+ *TODO:we dont need to do this here because its already done in
+ *validate_ccdc_config_params_raw
+ */
+ memcpy(&ccdc_hw_params_bayer.config_params,
+ &ccdc_raw_params,
+ sizeof(ccdc_raw_params));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+/* This function will configure CCDC for YCbCr parameters. */
+static int ccdc_config_ycbcr(void)
+{
+ struct ccdc_ycbcr_config *params = &ccdc_hw_params_ycbcr;
+ struct vpss_pg_frame_size frame_size;
+ u32 modeset = 0, ccdcfg = 0;
+ struct vpss_sync_pol sync;
+
+ /**
+ * first reset the CCDC
+ * all registers have default values after reset
+ * This is important since we assume default values to be set in
+ * a lot of registers that we didn't touch
+ */
+ dev_dbg(dev, "\nStarting ccdc_config_ycbcr...");
+ ccdc_restore_defaults();
+
+ /* configure pixel format or input mode */
+ modeset = modeset | ((params->pix_fmt & CCDC_INPUT_MASK)
+ << CCDC_INPUT_SHIFT) |
+ ((params->frm_fmt & CCDC_FRM_FMT_MASK) << CCDC_FRM_FMT_SHIFT) |
+ (((params->fid_pol & CCDC_FID_POL_MASK) << CCDC_FID_POL_SHIFT)) |
+ (((params->hd_pol & CCDC_HD_POL_MASK) << CCDC_HD_POL_SHIFT)) |
+ (((params->vd_pol & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT));
+
+ /* pack the data to 8-bit CCDCCFG */
+ switch (ccdc_if_type) {
+ case VPFE_BT656:
+ if (params->pix_fmt != CCDC_PIXFMT_YCBCR_8BIT) {
+ dev_err(dev, "Invalid pix_fmt(input mode)\n");
+ return -1;
+ }
+ modeset |=
+ ((VPFE_PINPOL_NEGATIVE & CCDC_VD_POL_MASK)
+ << CCDC_VD_POL_SHIFT);
+ regw(3, REC656IF);
+ ccdcfg = ccdcfg | CCDC_DATA_PACK8 | CCDC_YCINSWP_YCBCR;
+ break;
+ case VPFE_BT656_10BIT:
+ if (params->pix_fmt != CCDC_PIXFMT_YCBCR_8BIT) {
+ dev_err(dev, "Invalid pix_fmt(input mode)\n");
+ return -1;
+ }
+ /* setup BT.656, embedded sync */
+ regw(3, REC656IF);
+ /* enable 10 bit mode in ccdcfg */
+ ccdcfg = ccdcfg | CCDC_DATA_PACK8 | CCDC_YCINSWP_YCBCR |
+ CCDC_BW656_ENABLE;
+ break;
+ case VPFE_BT1120:
+ if (params->pix_fmt != CCDC_PIXFMT_YCBCR_16BIT) {
+ dev_err(dev, "Invalid pix_fmt(input mode)\n");
+ return -EINVAL;
+ }
+ regw(3, REC656IF);
+ break;
+
+ case VPFE_YCBCR_SYNC_8:
+ ccdcfg |= CCDC_DATA_PACK8;
+ ccdcfg |= CCDC_YCINSWP_YCBCR;
+ if (params->pix_fmt != CCDC_PIXFMT_YCBCR_8BIT) {
+ dev_err(dev, "Invalid pix_fmt(input mode)\n");
+ return -EINVAL;
+ }
+ break;
+ case VPFE_YCBCR_SYNC_16:
+ if (params->pix_fmt != CCDC_PIXFMT_YCBCR_16BIT) {
+ dev_err(dev, "Invalid pix_fmt(input mode)\n");
+ return -EINVAL;
+ }
+ break;
+ default:
+ /* should never come here */
+ dev_err(dev, "Invalid interface type\n");
+ return -EINVAL;
+ }
+
+ regw(modeset, MODESET);
+
+ /* Set up pix order */
+ ccdcfg |= (params->pix_order & CCDC_PIX_ORDER_MASK) <<
+ CCDC_PIX_ORDER_SHIFT;
+
+ regw(ccdcfg, CCDCFG);
+
+ /* configure video window */
+ if ((ccdc_if_type == VPFE_BT1120) ||
+ (ccdc_if_type == VPFE_YCBCR_SYNC_16))
+ ccdc_setwin(¶ms->win, params->frm_fmt, 1);
+ else
+ ccdc_setwin(¶ms->win, params->frm_fmt, 2);
+
+ /**
+ * configure the horizontal line offset
+ * this is done by rounding up width to a multiple of 16 pixels
+ * and multiply by two to account for y:cb:cr 4:2:2 data
+ */
+ regw(((((params->win.width * 2) + 31) & 0xffffffe0) >> 5), HSIZE);
+
+ /* configure the memory line offset */
+ if ((params->frm_fmt == CCDC_FRMFMT_INTERLACED) &&
+ (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED)) {
+ /* two fields are interleaved in memory */
+ regw(0x00000249, SDOFST);
+ }
+
+ /* Setup test pattern if enabled */
+ if (ccdc_hw_params_bayer.config_params.test_pat_gen) {
+ sync.ccdpg_hdpol = (params->hd_pol & CCDC_HD_POL_MASK);
+ sync.ccdpg_vdpol = (params->vd_pol & CCDC_VD_POL_MASK);
+ vpss_set_sync_pol(sync);
+ vpss_set_pg_frame_size(frame_size);
+ }
+
+ return 0;
+}
+
+static int ccdc_configure(void)
+{
+ if (ccdc_if_type == VPFE_RAW_BAYER)
+ return ccdc_config_raw(1);
+ else
+ ccdc_config_ycbcr();
+
+ return 0;
+}
+
+static int ccdc_close(struct device *device)
+{
+ /* copy defaults to module params */
+ memcpy(&ccdc_hw_params_bayer.config_params,
+ &ccdc_config_defaults,
+ sizeof(struct ccdc_config_params_raw));
+
+ return 0;
+}
+
+static struct ccdc_hw_device ccdc_hw_dev = {
+ .name = "DM365 ISIF",
+ .owner = THIS_MODULE,
+ .hw_ops = {
+ .open = ccdc_open,
+ .close = ccdc_close,
+ .set_ccdc_base = ccdc_set_ccdc_base,
+ .enable = ccdc_enable,
+ .enable_out_to_sdram = ccdc_enable_output_to_sdram,
+ .set_hw_if_params = ccdc_set_hw_if_params,
+ .set_params = ccdc_set_params,
+ .configure = ccdc_configure,
+ .set_buftype = ccdc_set_buftype,
+ .get_buftype = ccdc_get_buftype,
+ .enum_pix = ccdc_enum_pix,
+ .set_pixel_format = ccdc_set_pixel_format,
+ .get_pixel_format = ccdc_get_pixel_format,
+ .set_frame_format = ccdc_set_frame_format,
+ .get_frame_format = ccdc_get_frame_format,
+ .set_image_window = ccdc_set_image_window,
+ .get_image_window = ccdc_get_image_window,
+ .get_line_length = ccdc_get_line_length,
+ .setfbaddr = ccdc_setfbaddr,
+ .getfid = ccdc_getfid,
+ },
+};
+
+static int dm365_ccdc_init(void)
+{
+ int ret;
+ printk(KERN_NOTICE "dm365_ccdc_init\n");
+ davinci_cfg_reg(DM365_VIN_CAM_WEN);
+ davinci_cfg_reg(DM365_VIN_CAM_VD);
+ davinci_cfg_reg(DM365_VIN_CAM_HD);
+ davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
+ davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
+ ret = vpfe_register_ccdc_device(&ccdc_hw_dev);
+ if (ret < 0)
+ return ret;
+ printk(KERN_NOTICE "%s is registered with vpfe.\n",
+ ccdc_hw_dev.name);
+
+ return 0;
+}
+
+static void dm365_ccdc_exit(void)
+{
+ vpfe_unregister_ccdc_device(&ccdc_hw_dev);
+}
+
+module_init(dm365_ccdc_init);
+module_exit(dm365_ccdc_exit);
+
+
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/davinci/dm365_ccdc_regs.h b/drivers/media/video/davinci/dm365_ccdc_regs.h
new file mode 100644
index 0000000..d3f4b13
--- /dev/null
+++ b/drivers/media/video/davinci/dm365_ccdc_regs.h
@@ -0,0 +1,293 @@
+#ifndef _DM365_CCDC_REGS_H
+#define _DM365_CCDC_REGS_H
+
+/* ISIF registers relative offsets */
+#define SYNCEN 0x00
+#define MODESET 0x04
+#define HDW 0x08
+#define VDW 0x0c
+#define PPLN 0x10
+#define LPFR 0x14
+#define SPH 0x18
+#define LNH 0x1c
+#define SLV0 0x20
+#define SLV1 0x24
+#define LNV 0x28
+#define CULH 0x2c
+#define CULV 0x30
+#define HSIZE 0x34
+#define SDOFST 0x38
+#define CADU 0x3c
+#define CADL 0x40
+#define LINCFG0 0x44
+#define LINCFG1 0x48
+#define CCOLP 0x4c
+#define CRGAIN 0x50
+#define CGRGAIN 0x54
+#define CGBGAIN 0x58
+#define CBGAIN 0x5c
+#define COFSTA 0x60
+#define FLSHCFG0 0x64
+#define FLSHCFG1 0x68
+#define FLSHCFG2 0x6c
+#define VDINT0 0x70
+#define VDINT1 0x74
+#define VDINT2 0x78
+#define MISC 0x7c
+#define CGAMMAWD 0x80
+#define REC656IF 0x84
+#define CCDCFG 0x88
+/*****************************************************
+* Defect Correction registers
+*****************************************************/
+#define DFCCTL 0x8c
+#define VDFSATLV 0x90
+#define DFCMEMCTL 0x94
+#define DFCMEM0 0x98
+#define DFCMEM1 0x9c
+#define DFCMEM2 0xa0
+#define DFCMEM3 0xa4
+#define DFCMEM4 0xa8
+/****************************************************
+* Black Clamp registers
+****************************************************/
+#define CLAMPCFG 0xac
+#define CLDCOFST 0xb0
+#define CLSV 0xb4
+#define CLHWIN0 0xb8
+#define CLHWIN1 0xbc
+#define CLHWIN2 0xc0
+#define CLVRV 0xc4
+#define CLVWIN0 0xc8
+#define CLVWIN1 0xcc
+#define CLVWIN2 0xd0
+#define CLVWIN3 0xd4
+/****************************************************
+* Lense Shading Correction
+****************************************************/
+#define DATAHOFST 0xd8
+#define DATAVOFST 0xdc
+#define LSCHVAL 0xe0
+#define LSCVVAL 0xe4
+#define TWODLSCCFG 0xe8
+#define TWODLSCOFST 0xec
+#define TWODLSCINI 0xf0
+#define TWODLSCGRBU 0xf4
+#define TWODLSCGRBL 0xf8
+#define TWODLSCGROF 0xfc
+#define TWODLSCORBU 0x100
+#define TWODLSCORBL 0x104
+#define TWODLSCOROF 0x108
+#define TWODLSCIRQEN 0x10c
+#define TWODLSCIRQST 0x110
+/****************************************************
+* Data formatter
+****************************************************/
+#define FMTCFG 0x114
+#define FMTPLEN 0x118
+#define FMTSPH 0x11c
+#define FMTLNH 0x120
+#define FMTSLV 0x124
+#define FMTLNV 0x128
+#define FMTRLEN 0x12c
+#define FMTHCNT 0x130
+#define FMTAPTR_BASE 0x134
+/* Below macro for addresses FMTAPTR0 - FMTAPTR15 */
+#define FMTAPTR(i) (FMTAPTR_BASE + (i * 4))
+#define FMTPGMVF0 0x174
+#define FMTPGMVF1 0x178
+#define FMTPGMAPU0 0x17c
+#define FMTPGMAPU1 0x180
+#define FMTPGMAPS0 0x184
+#define FMTPGMAPS1 0x188
+#define FMTPGMAPS2 0x18c
+#define FMTPGMAPS3 0x190
+#define FMTPGMAPS4 0x194
+#define FMTPGMAPS5 0x198
+#define FMTPGMAPS6 0x19c
+#define FMTPGMAPS7 0x1a0
+/************************************************
+* Color Space Converter
+************************************************/
+#define CSCCTL 0x1a4
+#define CSCM0 0x1a8
+#define CSCM1 0x1ac
+#define CSCM2 0x1b0
+#define CSCM3 0x1b4
+#define CSCM4 0x1b8
+#define CSCM5 0x1bc
+#define CSCM6 0x1c0
+#define CSCM7 0x1c4
+#define OBWIN0 0x1c8
+#define OBWIN1 0x1cc
+#define OBWIN2 0x1d0
+#define OBWIN3 0x1d4
+#define OBVAL0 0x1d8
+#define OBVAL1 0x1dc
+#define OBVAL2 0x1e0
+#define OBVAL3 0x1e4
+#define OBVAL4 0x1e8
+#define OBVAL5 0x1ec
+#define OBVAL6 0x1f0
+#define OBVAL7 0x1f4
+#define CLKCTL 0x1f8
+
+#define CCDC_LINEAR_LUT0_ADDR 0x1C7C000
+#define CCDC_LINEAR_LUT1_ADDR 0x1C7C400
+
+/* Masks & Shifts below */
+#define START_PX_HOR_MASK (0x7FFF)
+#define NUM_PX_HOR_MASK (0x7FFF)
+#define START_VER_ONE_MASK (0x7FFF)
+#define START_VER_TWO_MASK (0x7FFF)
+#define NUM_LINES_VER (0x7FFF)
+
+/* gain - offset masks */
+#define GAIN_INTEGER_MASK (0x7)
+#define GAIN_INTEGER_SHIFT (0x9)
+#define GAIN_DECIMAL_MASK (0x1FF)
+#define OFFSET_MASK (0xFFF)
+#define GAIN_SDRAM_EN_SHIFT (12)
+#define GAIN_IPIPE_EN_SHIFT (13)
+#define GAIN_H3A_EN_SHIFT (14)
+#define OFST_SDRAM_EN_SHIFT (8)
+#define OFST_IPIPE_EN_SHIFT (9)
+#define OFST_H3A_EN_SHIFT (10)
+#define GAIN_OFFSET_EN_MASK (0x7700)
+
+/* Culling */
+#define CULL_PAT_EVEN_LINE_SHIFT (8)
+
+/* CCDCFG register */
+#define CCDC_YCINSWP_RAW (0x00 << 4)
+#define CCDC_YCINSWP_YCBCR (0x01 << 4)
+#define CCDC_CCDCFG_FIDMD_LATCH_VSYNC (0x00 << 6)
+#define CCDC_CCDCFG_WENLOG_AND (0x00 << 8)
+#define CCDC_CCDCFG_TRGSEL_WEN (0x00 << 9)
+#define CCDC_CCDCFG_EXTRG_DISABLE (0x00 << 10)
+#define CCDC_LATCH_ON_VSYNC_DISABLE (0x01 << 15)
+#define CCDC_LATCH_ON_VSYNC_ENABLE (0x00 << 15)
+#define CCDC_DATA_PACK_MASK (0x03)
+#define CCDC_DATA_PACK16 (0x0)
+#define CCDC_DATA_PACK12 (0x1)
+#define CCDC_DATA_PACK8 (0x2)
+#define CCDC_PIX_ORDER_SHIFT (11)
+#define CCDC_PIX_ORDER_MASK (0x01)
+#define CCDC_BW656_ENABLE (0x01 << 5)
+
+/* MODESET registers */
+#define CCDC_VDHDOUT_INPUT (0x00 << 0)
+#define CCDC_INPUT_MASK (0x03)
+#define CCDC_INPUT_SHIFT (12)
+#define CCDC_RAW_INPUT_MODE (0x00)
+#define CCDC_FID_POL_MASK (0x01)
+#define CCDC_FID_POL_SHIFT (4)
+#define CCDC_HD_POL_MASK (0x01)
+#define CCDC_HD_POL_SHIFT (3)
+#define CCDC_VD_POL_MASK (0x01)
+#define CCDC_VD_POL_SHIFT (2)
+#define CCDC_DATAPOL_NORMAL (0x00)
+#define CCDC_DATAPOL_MASK (0x01)
+#define CCDC_DATAPOL_SHIFT (6)
+#define CCDC_EXWEN_DISABLE (0x00)
+#define CCDC_EXWEN_MASK (0x01)
+#define CCDC_EXWEN_SHIFT (5)
+#define CCDC_FRM_FMT_MASK (0x01)
+#define CCDC_FRM_FMT_SHIFT (7)
+#define CCDC_DATASFT_MASK (0x07)
+#define CCDC_DATASFT_SHIFT (8)
+#define CCDC_LPF_SHIFT (14)
+#define CCDC_LPF_MASK (0x1)
+
+/* GAMMAWD registers */
+#define CCDC_ALAW_GAMA_WD_MASK (0xF)
+#define CCDC_ALAW_GAMA_WD_SHIFT (1)
+#define CCDC_ALAW_ENABLE (0x01)
+#define CCDC_GAMMAWD_CFA_MASK (0x01)
+#define CCDC_GAMMAWD_CFA_SHIFT (5)
+
+/* HSIZE registers */
+#define CCDC_HSIZE_FLIP_MASK (0x01)
+#define CCDC_HSIZE_FLIP_SHIFT (12)
+#define CCDC_LINEOFST_MASK (0xFFF)
+
+/* MISC registers */
+#define CCDC_DPCM_EN_SHIFT (12)
+#define CCDC_DPCM_EN_MASK (1)
+#define CCDC_DPCM_PREDICTOR_SHIFT (13)
+#define CCDC_DPCM_PREDICTOR_MASK (1)
+
+/* Black clamp related */
+#define CCDC_BC_DCOFFSET_MASK (0x1FFF)
+#define CCDC_BC_MODE_COLOR_MASK (1)
+#define CCDC_BC_MODE_COLOR_SHIFT (4)
+#define CCDC_HORZ_BC_MODE_MASK (3)
+#define CCDC_HORZ_BC_MODE_SHIFT (1)
+#define CCDC_HORZ_BC_WIN_COUNT_MASK (0x1F)
+#define CCDC_HORZ_BC_WIN_SEL_SHIFT (5)
+#define CCDC_HORZ_BC_PIX_LIMIT_SHIFT (6)
+#define CCDC_HORZ_BC_WIN_H_SIZE_MASK (3)
+#define CCDC_HORZ_BC_WIN_H_SIZE_SHIFT (8)
+#define CCDC_HORZ_BC_WIN_V_SIZE_MASK (3)
+#define CCDC_HORZ_BC_WIN_V_SIZE_SHIFT (12)
+#define CCDC_HORZ_BC_WIN_START_H_MASK (0x1FFF)
+#define CCDC_HORZ_BC_WIN_START_V_MASK (0x1FFF)
+#define CCDC_VERT_BC_OB_H_SZ_MASK (7)
+#define CCDC_VERT_BC_RST_VAL_SEL_MASK (3)
+#define CCDC_VERT_BC_RST_VAL_SEL_SHIFT (4)
+#define CCDC_VERT_BC_LINE_AVE_COEF_SHIFT (8)
+#define CCDC_VERT_BC_OB_START_HORZ_MASK (0x1FFF)
+#define CCDC_VERT_BC_OB_START_VERT_MASK (0x1FFF)
+#define CCDC_VERT_BC_OB_VERT_SZ_MASK (0x1FFF)
+#define CCDC_VERT_BC_RST_VAL_MASK (0xFFF)
+#define CCDC_BC_VERT_START_SUB_V_MASK (0x1FFF)
+
+/* VDFC registers */
+#define CCDC_VDFC_EN_SHIFT (4)
+#define CCDC_VDFC_CORR_MOD_MASK (3)
+#define CCDC_VDFC_CORR_MOD_SHIFT (5)
+#define CCDC_VDFC_CORR_WHOLE_LN_SHIFT (7)
+#define CCDC_VDFC_LEVEL_SHFT_MASK (7)
+#define CCDC_VDFC_LEVEL_SHFT_SHIFT (8)
+#define CCDC_VDFC_SAT_LEVEL_MASK (0xFFF)
+#define CCDC_VDFC_POS_MASK (0x1FFF)
+#define CCDC_DFCMEMCTL_DFCMARST_SHIFT (2)
+
+/* CSC registers */
+#define CCDC_CSC_COEF_INTEG_MASK (7)
+#define CCDC_CSC_COEF_DECIMAL_MASK (0x1f)
+#define CCDC_CSC_COEF_INTEG_SHIFT (5)
+#define CCDC_CSCM_MSB_SHIFT (8)
+#define CCDC_DF_CSC_SPH_MASK (0x1FFF)
+#define CCDC_DF_CSC_LNH_MASK (0x1FFF)
+#define CCDC_DF_CSC_SLV_MASK (0x1FFF)
+#define CCDC_DF_CSC_LNV_MASK (0x1FFF)
+#define CCDC_DF_NUMLINES (0x7FFF)
+#define CCDC_DF_NUMPIX (0x1FFF)
+
+/* Offsets for LSC/DFC/Gain */
+#define CCDC_DATA_H_OFFSET_MASK (0x1FFF)
+#define CCDC_DATA_V_OFFSET_MASK (0x1FFF)
+
+/* Linearization */
+#define CCDC_LIN_CORRSFT_MASK (7)
+#define CCDC_LIN_CORRSFT_SHIFT (4)
+#define CCDC_LIN_SCALE_FACT_INTEG_SHIFT (10)
+#define CCDC_LIN_SCALE_FACT_DECIMAL_MASK (0x3FF)
+#define CCDC_LIN_ENTRY_MASK (0x3FF)
+
+#define CCDC_DF_FMTRLEN_MASK (0x1FFF)
+#define CCDC_DF_FMTHCNT_MASK (0x1FFF)
+
+/* Pattern registers */
+#define CCDC_PG_EN (1 << 3)
+#define CCDC_SEL_PG_SRC (3 << 4)
+#define CCDC_PG_VD_POL_SHIFT (0)
+#define CCDC_PG_HD_POL_SHIFT (1)
+
+/*random other junk*/
+#define CCDC_SYNCEN_VDHDEN_MASK (1 << 0)
+#define CCDC_SYNCEN_WEN_MASK (1 << 1)
+#define CCDC_SYNCEN_WEN_SHIFT 1
+
+#endif
diff --git a/include/media/davinci/dm365_ccdc.h b/include/media/davinci/dm365_ccdc.h
new file mode 100644
index 0000000..156e139
--- /dev/null
+++ b/include/media/davinci/dm365_ccdc.h
@@ -0,0 +1,722 @@
+/*
+ * Copyright (C) 2008-2009 Texas Instruments Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * ccdc header file for DM365 ISIF
+ */
+
+#ifndef _DM365_CCDC_H
+#define _DM365_CCDC_H
+#include <media/davinci/ccdc_types.h>
+#include <media/davinci/vpfe_types.h>
+/**
+ * ccdc float type S8Q8/U8Q8
+ */
+struct ccdc_float_8 {
+ /* 8 bit integer part */
+ unsigned char integer;
+ /* 8 bit decimal part */
+ unsigned char decimal;
+};
+
+/**
+ * brief ccdc float type U16Q16/S16Q16
+ */
+struct ccdc_float_16 {
+ /* 16 bit integer part */
+ unsigned short integer;
+ /* 16 bit decimal part */
+ unsigned short decimal;
+};
+
+/*
+ * ccdc image(target) window parameters
+ */
+struct ccdc_cropwin {
+ /* horzontal offset of the top left corner in pixels */
+ unsigned int left;
+ /* vertical offset of the top left corner in pixels */
+ unsigned int top;
+ /* width in pixels of the rectangle */
+ unsigned int width;
+ /* height in lines of the rectangle */
+ unsigned int height;
+};
+
+/************************************************************************
+ * Vertical Defect Correction parameters
+ ***********************************************************************/
+
+/**
+ * vertical defect correction methods
+ */
+enum ccdc_vdfc_corr_mode {
+ /* Defect level subtraction. Just fed through if saturating */
+ CCDC_VDFC_NORMAL,
+ /**
+ * Defect level subtraction. Horizontal interpolation ((i-2)+(i+2))/2
+ * if data saturating
+ */
+ CCDC_VDFC_HORZ_INTERPOL_IF_SAT,
+ /* Horizontal interpolation (((i-2)+(i+2))/2) */
+ CCDC_VDFC_HORZ_INTERPOL
+};
+
+/**
+ * Max Size of the Vertical Defect Correction table
+ */
+#define CCDC_VDFC_TABLE_SIZE 8
+
+/**
+ * Values used for shifting up the vdfc defect level
+ */
+enum ccdc_vdfc_shift {
+ /* No Shift */
+ CCDC_VDFC_NO_SHIFT,
+ /* Shift by 1 bit */
+ CCDC_VDFC_SHIFT_1,
+ /* Shift by 2 bit */
+ CCDC_VDFC_SHIFT_2,
+ /* Shift by 3 bit */
+ CCDC_VDFC_SHIFT_3,
+ /* Shift by 4 bit */
+ CCDC_VDFC_SHIFT_4
+};
+
+/**
+ * Defect Correction (DFC) table entry
+ */
+struct ccdc_vdfc_entry {
+ /* vertical position of defect */
+ unsigned short pos_vert;
+ /* horizontal position of defect */
+ unsigned short pos_horz;
+ /**
+ * Defect level of Vertical line defect position. This is subtracted
+ * from the data at the defect position
+ */
+ unsigned char level_at_pos;
+ /**
+ * Defect level of the pixels upper than the vertical line defect.
+ * This is subtracted from the data
+ */
+ unsigned char level_up_pixels;
+ /**
+ * Defect level of the pixels lower than the vertical line defect.
+ * This is subtracted from the data
+ */
+ unsigned char level_low_pixels;
+};
+
+/**
+ * Structure for Defect Correction (DFC) parameter
+ */
+struct ccdc_dfc {
+ /* enable vertical defect correction */
+ unsigned char en;
+ /* Correction methods */
+ enum ccdc_vdfc_corr_mode corr_mode;
+ /**
+ * 0 - whole line corrected, 1 - not
+ * pixels upper than the defect
+ */
+ unsigned char corr_whole_line;
+ /**
+ * defect level shift value. level_at_pos, level_upper_pos,
+ * and level_lower_pos can be shifted up by this value
+ */
+ enum ccdc_vdfc_shift def_level_shift;
+ /* defect saturation level */
+ unsigned short def_sat_level;
+ /* number of vertical defects. Max is CCDC_VDFC_TABLE_SIZE */
+ short num_vdefects;
+ /* VDFC table ptr */
+ struct ccdc_vdfc_entry table[CCDC_VDFC_TABLE_SIZE];
+};
+
+/************************************************************************
+* Digital/Black clamp or DC Subtract parameters
+************************************************************************/
+/**
+ * Horizontal Black Clamp modes
+ */
+enum ccdc_horz_bc_mode {
+ /**
+ * Horizontal clamp disabled. Only vertical clamp
+ * value is subtracted
+ */
+ CCDC_HORZ_BC_DISABLE,
+ /**
+ * Horizontal clamp value is calculated and subtracted
+ * from image data along with vertical clamp value
+ */
+ CCDC_HORZ_BC_CLAMP_CALC_ENABLED,
+ /**
+ * Horizontal clamp value calculated from previous image
+ * is subtracted from image data along with vertical clamp
+ * value. How the horizontal clamp value for the first image
+ * is calculated in this case ???
+ */
+ CCDC_HORZ_BC_CLAMP_NOT_UPDATED
+};
+
+/**
+ * Base window selection for Horizontal Black Clamp calculations
+ */
+enum ccdc_horz_bc_base_win_sel {
+ /* Select Most left window for bc calculation */
+ CCDC_SEL_MOST_LEFT_WIN,
+
+ /* Select Most right window for bc calculation */
+ CCDC_SEL_MOST_RIGHT_WIN,
+};
+
+/* Size of window in horizontal direction for horizontal bc */
+enum ccdc_horz_bc_sz_h {
+ CCDC_HORZ_BC_SZ_H_2PIXELS,
+ CCDC_HORZ_BC_SZ_H_4PIXELS,
+ CCDC_HORZ_BC_SZ_H_8PIXELS,
+ CCDC_HORZ_BC_SZ_H_16PIXELS
+};
+
+/* Size of window in vertcal direction for vertical bc */
+enum ccdc_horz_bc_sz_v {
+ CCDC_HORZ_BC_SZ_H_32PIXELS,
+ CCDC_HORZ_BC_SZ_H_64PIXELS,
+ CCDC_HORZ_BC_SZ_H_128PIXELS,
+ CCDC_HORZ_BC_SZ_H_256PIXELS
+};
+
+/**
+ * Structure for Horizontal Black Clamp config params
+ */
+struct ccdc_horz_bclamp {
+ /* horizontal clamp mode */
+ enum ccdc_horz_bc_mode mode;
+ /**
+ * pixel value limit enable.
+ * 0 - limit disabled
+ * 1 - pixel value limited to 1023
+ */
+ unsigned char clamp_pix_limit;
+ /**
+ * Select most left or right window for clamp val
+ * calculation
+ */
+ enum ccdc_horz_bc_base_win_sel base_win_sel_calc;
+ /* Window count per color for calculation. range 1-32 */
+ unsigned char win_count_calc;
+ /* Window start position - horizontal for calculation. 0 - 8191 */
+ unsigned short win_start_h_calc;
+ /* Window start position - vertical for calculation 0 - 8191 */
+ unsigned short win_start_v_calc;
+ /* Width of the sample window in pixels for calculation */
+ enum ccdc_horz_bc_sz_h win_h_sz_calc;
+ /* Height of the sample window in pixels for calculation */
+ enum ccdc_horz_bc_sz_v win_v_sz_calc;
+};
+
+/**
+ * Black Clamp vertical reset values
+ */
+enum ccdc_vert_bc_reset_val_sel {
+ /* Reset value used is the clamp value calculated */
+ CCDC_VERT_BC_USE_HORZ_CLAMP_VAL,
+ /* Reset value used is reset_clamp_val configured */
+ CCDC_VERT_BC_USE_CONFIG_CLAMP_VAL,
+ /* No update, previous image value is used */
+ CCDC_VERT_BC_NO_UPDATE
+};
+
+enum ccdc_vert_bc_sz_h {
+ CCDC_VERT_BC_SZ_H_2PIXELS,
+ CCDC_VERT_BC_SZ_H_4PIXELS,
+ CCDC_VERT_BC_SZ_H_8PIXELS,
+ CCDC_VERT_BC_SZ_H_16PIXELS,
+ CCDC_VERT_BC_SZ_H_32PIXELS,
+ CCDC_VERT_BC_SZ_H_64PIXELS
+};
+
+/**
+ * Structure for Vetical Black Clamp configuration params
+ */
+struct ccdc_vert_bclamp {
+ /* Reset value selection for vertical clamp calculation */
+ enum ccdc_vert_bc_reset_val_sel reset_val_sel;
+ /* U12 value if reset_sel = CCDC_BC_VERT_USE_CONFIG_CLAMP_VAL */
+ unsigned short reset_clamp_val;
+ /**
+ * U8Q8. Line average coefficient used in vertical clamp
+ * calculation
+ */
+ unsigned char line_ave_coef;
+ /* Width in pixels of the optical black region used for calculation. */
+ enum ccdc_vert_bc_sz_h ob_h_sz_calc;
+ /* Height of the optical black region for calculation */
+ unsigned short ob_v_sz_calc;
+ /* Optical black region start position - horizontal. 0 - 8191 */
+ unsigned short ob_start_h;
+ /* Optical black region start position - vertical 0 - 8191 */
+ unsigned short ob_start_v;
+};
+
+/**
+ * Structure for Black Clamp configuration params
+ */
+struct ccdc_black_clamp {
+ /**
+ * this offset value is added irrespective of the clamp
+ * enable status. S13
+ */
+ unsigned short dc_offset;
+ /**
+ * Enable black/digital clamp value to be subtracted
+ * from the image data
+ */
+ unsigned char en;
+ /**
+ * black clamp mode. same/separate clamp for 4 colors
+ * 0 - disable - same clamp value for all colors
+ * 1 - clamp value calculated separately for all colors
+ */
+ unsigned char bc_mode_color;
+ /* Vrtical start position for bc subtraction */
+ unsigned short vert_start_sub;
+ /* Black clamp for horizontal direction */
+ struct ccdc_horz_bclamp horz;
+ /* Black clamp for vertical direction */
+ struct ccdc_vert_bclamp vert;
+};
+
+/*************************************************************************
+** Color Space Convertion (CSC)
+*************************************************************************/
+/**
+ * Number of Coefficient values used for CSC
+ */
+#define CCDC_CSC_NUM_COEFF 16
+
+/*************************************************************************
+** Color Space Conversion parameters
+*************************************************************************/
+/**
+ * Structure used for CSC config params
+ */
+struct ccdc_color_space_conv {
+ /* Enable color space conversion */
+ unsigned char en;
+ /**
+ * csc coeffient table. S8Q5, M00 at index 0, M01 at index 1, and
+ * so forth
+ */
+ struct ccdc_float_8 coeff[CCDC_CSC_NUM_COEFF];
+};
+
+/**
+ * CCDC image data size
+ */
+enum ccdc_data_size {
+ /* 8 bits */
+ CCDC_8_BITS,
+ /* 9 bits */
+ CCDC_9_BITS,
+ /* 10 bits */
+ CCDC_10_BITS,
+ /* 11 bits */
+ CCDC_11_BITS,
+ /* 12 bits */
+ CCDC_12_BITS,
+ /* 13 bits */
+ CCDC_13_BITS,
+ /* 14 bits */
+ CCDC_14_BITS,
+ /* 15 bits */
+ CCDC_15_BITS,
+ /* 16 bits */
+ CCDC_16_BITS
+};
+
+/**
+ * CCDC image data shift to right
+ */
+enum ccdc_datasft {
+ /* No Shift */
+ CCDC_NO_SHIFT,
+ /* 1 bit Shift */
+ CCDC_1BIT_SHIFT,
+ /* 2 bit Shift */
+ CCDC_2BIT_SHIFT,
+ /* 3 bit Shift */
+ CCDC_3BIT_SHIFT,
+ /* 4 bit Shift */
+ CCDC_4BIT_SHIFT,
+ /* 5 bit Shift */
+ CCDC_5BIT_SHIFT,
+ /* 6 bit Shift */
+ CCDC_6BIT_SHIFT
+};
+
+/**
+ * MSB of image data connected to sensor port
+ */
+enum ccdc_data_msb {
+ /* MSB b15 */
+ CCDC_BIT_MSB_15,
+ /* MSB b14 */
+ CCDC_BIT_MSB_14,
+ /* MSB b13 */
+ CCDC_BIT_MSB_13,
+ /* MSB b12 */
+ CCDC_BIT_MSB_12,
+ /* MSB b11 */
+ CCDC_BIT_MSB_11,
+ /* MSB b10 */
+ CCDC_BIT_MSB_10,
+ /* MSB b9 */
+ CCDC_BIT_MSB_9,
+ /* MSB b8 */
+ CCDC_BIT_MSB_8,
+ /* MSB b7 */
+ CCDC_BIT_MSB_7
+};
+
+/*************************************************************************
+** Black Compensation parameters
+*************************************************************************/
+/**
+ * Structure used for Black Compensation
+ */
+struct ccdc_black_comp {
+ /* Comp for Red */
+ char r_comp;
+ /* Comp for Gr */
+ char gr_comp;
+ /* Comp for Blue */
+ char b_comp;
+ /* Comp for Gb */
+ char gb_comp;
+};
+
+/*************************************************************************
+** Gain parameters
+*************************************************************************/
+/**
+ * Structure for Gain parameters
+ */
+struct ccdc_gain {
+ /* Gain for Red or ye */
+ struct ccdc_float_16 r_ye;
+ /* Gain for Gr or cy */
+ struct ccdc_float_16 gr_cy;
+ /* Gain for Gb or g */
+ struct ccdc_float_16 gb_g;
+ /* Gain for Blue or mg */
+ struct ccdc_float_16 b_mg;
+};
+
+/**
+ * Predicator types for DPCM compression
+ */
+enum ccdc_dpcm_predictor {
+ /* Choose Predictor1 for DPCM compression */
+ CCDC_DPCM_PRED1,
+ /* Choose Predictor2 for DPCM compression */
+ CCDC_DPCM_PRED2
+};
+
+#define CCDC_LINEAR_TAB_SIZE 192
+/*************************************************************************
+** Linearization parameters
+*************************************************************************/
+/**
+ * Structure for Sensor data linearization
+ */
+struct ccdc_linearize {
+ /* Enable or Disable linearization of data */
+ unsigned char en;
+ /* Shift value applied */
+ enum ccdc_datasft corr_shft;
+ /* scale factor applied U11Q10 */
+ struct ccdc_float_16 scale_fact;
+ /* Size of the linear table */
+ unsigned short table[CCDC_LINEAR_TAB_SIZE];
+};
+
+enum ccdc_cfa_pattern {
+ CCDC_CFA_PAT_MOSAIC,
+ CCDC_CFA_PAT_STRIPE
+};
+
+enum ccdc_colpats {
+ CCDC_RED,
+ CCDC_GREEN_RED,
+ CCDC_GREEN_BLUE,
+ CCDC_BLUE
+};
+
+struct ccdc_col_pat {
+ enum ccdc_colpats olop;
+ enum ccdc_colpats olep;
+ enum ccdc_colpats elop;
+ enum ccdc_colpats elep;
+};
+
+/*************************************************************************
+** CCDC Raw configuration parameters
+*************************************************************************/
+enum ccdc_fmt_mode {
+ CCDC_SPLIT,
+ CCDC_COMBINE
+};
+
+enum ccdc_lnum {
+ CCDC_1LINE,
+ CCDC_2LINES,
+ CCDC_3LINES,
+ CCDC_4LINES
+};
+
+enum ccdc_line {
+ CCDC_1STLINE,
+ CCDC_2NDLINE,
+ CCDC_3RDLINE,
+ CCDC_4THLINE
+};
+
+struct ccdc_fmtplen {
+ /**
+ * number of program entries for SET0, range 1 - 16
+ * when fmtmode is CCDC_SPLIT, 1 - 8 when fmtmode is
+ * CCDC_COMBINE
+ */
+ unsigned short plen0;
+ /**
+ * number of program entries for SET1, range 1 - 16
+ * when fmtmode is CCDC_SPLIT, 1 - 8 when fmtmode is
+ * CCDC_COMBINE
+ */
+ unsigned short plen1;
+ /**
+ * number of program entries for SET2, range 1 - 16
+ * when fmtmode is CCDC_SPLIT, 1 - 8 when fmtmode is
+ * CCDC_COMBINE
+ */
+ unsigned short plen2;
+ /**
+ * number of program entries for SET3, range 1 - 16
+ * when fmtmode is CCDC_SPLIT, 1 - 8 when fmtmode is
+ * CCDC_COMBINE
+ */
+ unsigned short plen3;
+};
+
+struct ccdc_fmt_cfg {
+ /* Split or combine or line alternate */
+ enum ccdc_fmt_mode fmtmode;
+ /* enable or disable line alternating mode */
+ unsigned char ln_alter_en;
+ /* Split/combine line number */
+ enum ccdc_lnum lnum;
+ /* Address increment Range 1 - 16 */
+ unsigned int addrinc;
+};
+
+struct ccdc_fmt_addr_ptr {
+ /* Initial address */
+ unsigned int init_addr;
+ /* output line number */
+ enum ccdc_line out_line;
+};
+
+struct ccdc_fmtpgm_ap {
+ /* program address pointer */
+ unsigned char pgm_aptr;
+ /* program address increment or decrement */
+ unsigned char pgmupdt;
+};
+
+struct ccdc_data_formatter {
+ /* Enable/Disable data formatter */
+ unsigned char en;
+ /* data formatter configuration */
+ struct ccdc_fmt_cfg cfg;
+ /* Formatter program entries length */
+ struct ccdc_fmtplen plen;
+ /* first pixel in a line fed to formatter */
+ unsigned short fmtrlen;
+ /* HD interval for output line. Only valid when split line */
+ unsigned short fmthcnt;
+ /* formatter address pointers */
+ struct ccdc_fmt_addr_ptr fmtaddr_ptr[16];
+ /* program enable/disable */
+ unsigned char pgm_en[32];
+ /* program address pointers */
+ struct ccdc_fmtpgm_ap fmtpgm_ap[32];
+};
+
+struct ccdc_df_csc {
+ /* Color Space Conversion confguration, 0 - csc, 1 - df */
+ unsigned int df_or_csc;
+ /* csc configuration valid if df_or_csc is 0 */
+ struct ccdc_color_space_conv csc;
+ /* data formatter configuration valid if df_or_csc is 1 */
+ struct ccdc_data_formatter df;
+ /* start pixel in a line at the input */
+ unsigned int start_pix;
+ /* number of pixels in input line */
+ unsigned int num_pixels;
+ /* start line at the input */
+ unsigned int start_line;
+ /* number of lines at the input */
+ unsigned int num_lines;
+};
+
+struct ccdc_gain_offsets_adj {
+ /* Gain adjustment per color */
+ struct ccdc_gain gain;
+ /* Offset adjustment */
+ unsigned short offset;
+ /* Enable or Disable Gain adjustment for SDRAM data */
+ unsigned char gain_sdram_en;
+ /* Enable or Disable Gain adjustment for IPIPE data */
+ unsigned char gain_ipipe_en;
+ /* Enable or Disable Gain adjustment for H3A data */
+ unsigned char gain_h3a_en;
+ /* Enable or Disable Gain adjustment for SDRAM data */
+ unsigned char offset_sdram_en;
+ /* Enable or Disable Gain adjustment for IPIPE data */
+ unsigned char offset_ipipe_en;
+ /* Enable or Disable Gain adjustment for H3A data */
+ unsigned char offset_h3a_en;
+};
+
+struct ccdc_cul {
+ /* Horizontal Cull pattern for odd lines */
+ unsigned char hcpat_odd;
+ /* Horizontal Cull pattern for even lines */
+ unsigned char hcpat_even;
+ /* Vertical Cull pattern */
+ unsigned char vcpat;
+ /* Enable or disable lpf. Apply when cull is enabled */
+ unsigned char en_lpf;
+};
+
+enum ccdc_compress_alg {
+ CCDC_ALAW,
+ CCDC_DPCM,
+ CCDC_NO_COMPRESSION
+};
+
+struct ccdc_compress {
+ /* Enable or diable A-Law or DPCM compression. */
+ enum ccdc_compress_alg alg;
+ /* Predictor for DPCM compression */
+ enum ccdc_dpcm_predictor pred;
+};
+
+/* all the stuff in this struct will be provided by userland */
+struct ccdc_config_params_raw {
+ /* Linearization parameters for image sensor data input */
+ struct ccdc_linearize linearize;
+ /* Data formatter or CSC */
+ struct ccdc_df_csc df_csc;
+ /* Defect Pixel Correction (DFC) confguration */
+ struct ccdc_dfc dfc;
+ /* Black/Digital Clamp configuration */
+ struct ccdc_black_clamp bclamp;
+ /* Gain, offset adjustments */
+ struct ccdc_gain_offsets_adj gain_offset;
+ /* Culling */
+ struct ccdc_cul culling;
+ /* A-Law and DPCM compression options */
+ struct ccdc_compress compress;
+ /* horizontal offset for Gain/LSC/DFC */
+ unsigned short horz_offset;
+ /* vertical offset for Gain/LSC/DFC */
+ unsigned short vert_offset;
+ /* color pattern for field 0 */
+ struct ccdc_col_pat col_pat_field0;
+ /* color pattern for field 1 */
+ struct ccdc_col_pat col_pat_field1;
+ /* data size from 8 to 16 bits */
+ enum ccdc_data_size data_size;
+ /* Data shift applied before storing to SDRAM */
+ enum ccdc_datasft data_shift;
+ /* enable input test pattern generation */
+ unsigned char test_pat_gen;
+};
+
+#ifdef __KERNEL__
+struct ccdc_ycbcr_config {
+ /* ccdc pixel format */
+ enum ccdc_pixfmt pix_fmt;
+ /* ccdc frame format */
+ enum ccdc_frmfmt frm_fmt;
+ /* CCDC crop window */
+ struct v4l2_rect win;
+ /* field polarity */
+ enum vpfe_pin_pol fid_pol;
+ /* interface VD polarity */
+ enum vpfe_pin_pol vd_pol;
+ /* interface HD polarity */
+ enum vpfe_pin_pol hd_pol;
+ /* ccdc pix order. Only used for ycbcr capture */
+ enum ccdc_pixorder pix_order;
+ /* ccdc buffer type. Only used for ycbcr capture */
+ enum ccdc_buftype buf_type;
+};
+
+struct ccdc_params_raw {
+ /* ccdc pixel format */
+ enum ccdc_pixfmt pix_fmt;
+ /* ccdc frame format */
+ enum ccdc_frmfmt frm_fmt;
+ /* video window */
+ struct v4l2_rect win;
+ /* field polarity */
+ enum vpfe_pin_pol fid_pol;
+ /* interface VD polarity */
+ enum vpfe_pin_pol vd_pol;
+ /* interface HD polarity */
+ enum vpfe_pin_pol hd_pol;
+ /* buffer type. Applicable for interlaced mode */
+ enum ccdc_buftype buf_type;
+ /* Gain values */
+ struct ccdc_gain gain;
+ /* cfa pattern */
+ enum ccdc_cfa_pattern cfa_pat;
+ /* Data MSB position */
+ enum ccdc_data_msb data_msb;
+ /* Enable horizontal flip */
+ unsigned char horz_flip_en;
+ /* Enable image invert vertically */
+ unsigned char image_invert_en;
+
+ /*all the userland defined stuff*/
+ struct ccdc_config_params_raw config_params;
+};
+
+enum ccdc_data_pack {
+ CCDC_PACK_16BIT,
+ CCDC_PACK_12BIT,
+ CCDC_PACK_8BIT
+};
+
+#define CCDC_WIN_NTSC {0, 0, 720, 480}
+#define CCDC_WIN_VGA {0, 0, 640, 480}
+#define ISP5_CCDCMUX 0x20
+#endif
+#endif
--
1.6.0.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v1 4/4] Build system support for DM365 CCDC
2009-08-17 20:05 ` [PATCH v1 3/4] CCDC support on DM365 neilsikka
@ 2009-08-17 20:05 ` neilsikka
0 siblings, 0 replies; 8+ messages in thread
From: neilsikka @ 2009-08-17 20:05 UTC (permalink / raw)
To: linux-media, davinci-linux-open-source; +Cc: khilman, hverkuil, Neil Sikka
From: Neil Sikka <neilsikka@ti.com>
This patch sets up the build system for DM365 VPFE support
Reviewed-by: Muralidharan Karicheri <m-karicheri2@ti.com>
Mandatory-Reviewer: Hans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: Neil Sikka <neilsikka@ti.com>
---
Applies to v4l-dvb linux-next repository
drivers/media/video/Kconfig | 9 +++++++++
drivers/media/video/davinci/Makefile | 3 ++-
2 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index 1fa3c87..e0dd402 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -578,6 +578,15 @@ config VIDEO_DM355_CCDC
To compile this driver as a module, choose M here: the
module will be called vpfe.
+config VIDEO_DM365_ISIF
+ tristate "DM365 CCDC/ISIF HW module"
+ depends on ARCH_DAVINCI_DM365 && VIDEO_VPFE_CAPTURE
+ default y
+ help
+ Enables DM365 ISIF hw module. This is the hardware module for
+ configuring ISIF in VPFE to capture Raw Bayer RGB data from
+ a image sensor or YUV data from a YUV source.
+
source "drivers/media/video/bt8xx/Kconfig"
config VIDEO_PMS
diff --git a/drivers/media/video/davinci/Makefile b/drivers/media/video/davinci/Makefile
index f44cad2..5f4c830 100644
--- a/drivers/media/video/davinci/Makefile
+++ b/drivers/media/video/davinci/Makefile
@@ -8,8 +8,9 @@ obj-$(CONFIG_VIDEO_DAVINCI_VPIF) += vpif.o
#DM646x EVM Display driver
obj-$(CONFIG_DISPLAY_DAVINCI_DM646X_EVM) += vpif_display.o
-# Capture: DM6446 and DM355
+# Capture: DM6446, DM355, DM365
obj-$(CONFIG_VIDEO_VPSS_SYSTEM) += vpss.o
obj-$(CONFIG_VIDEO_VPFE_CAPTURE) += vpfe_capture.o
obj-$(CONFIG_VIDEO_DM6446_CCDC) += dm644x_ccdc.o
obj-$(CONFIG_VIDEO_DM355_CCDC) += dm355_ccdc.o
+obj-$(CONFIG_VIDEO_DM365_ISIF) += dm365_ccdc.o
--
1.6.0.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v1 1/4] DM365 Platform support for VPFE
2009-08-17 20:05 ` [PATCH v1 1/4] DM365 Platform support for VPFE neilsikka
2009-08-17 20:05 ` [PATCH v1 2/4] DM365 VPSS support neilsikka
@ 2009-10-15 23:18 ` Kevin Hilman
2009-10-16 15:29 ` Karicheri, Muralidharan
1 sibling, 1 reply; 8+ messages in thread
From: Kevin Hilman @ 2009-10-15 23:18 UTC (permalink / raw)
To: neilsikka; +Cc: linux-media, davinci-linux-open-source, hverkuil
neilsikka@ti.com writes:
> From: Neil Sikka <neilsikka@ti.com>
>
> This has platform and board setup changes to support the vpfe capture
> driver for DM365 EVMs.
>
> Reviewed-by: Muralidharan Karicheri <m-karicheri2@ti.com>
> Mandatory-Reviewer: Hans Verkuil <hverkuil@xs4all.nl>
> Mandatory-Reviewer: Kevin Hilman <khilman@deeprootsystems.com>
> Signed-off-by: Neil Sikka <neilsikka@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
for this patch, but the rest of the series needs to be reviewed by linux-media folks.
Kevin
> ---
> Applies to Kevin Hilman's linux-davinci repository
> arch/arm/mach-davinci/board-dm365-evm.c | 71 ++++++++++++++++++++++++++++
> arch/arm/mach-davinci/dm365.c | 68 ++++++++++++++++++++++++++
> arch/arm/mach-davinci/include/mach/dm365.h | 2 +
> 3 files changed, 141 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
> index f6adf79..757ad13 100644
> --- a/arch/arm/mach-davinci/board-dm365-evm.c
> +++ b/arch/arm/mach-davinci/board-dm365-evm.c
> @@ -38,6 +38,8 @@
> #include <mach/common.h>
> #include <mach/mmc.h>
> #include <mach/nand.h>
> +#include <linux/videodev2.h>
> +#include <media/tvp514x.h>
>
>
> static inline int have_imager(void)
> @@ -98,6 +100,11 @@ static inline int have_tvp7002(void)
>
> static void __iomem *cpld;
>
> +static struct tvp514x_platform_data tvp5146_pdata = {
> + .clk_polarity = 0,
> + .hs_polarity = 1,
> + .vs_polarity = 1
> +};
>
> /* NOTE: this is geared for the standard config, with a socketed
> * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
> @@ -210,6 +217,68 @@ static int cpld_mmc_get_ro(int module)
> return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
> }
>
> +#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
> +/* Inputs available at the TVP5146 */
> +static struct v4l2_input tvp5146_inputs[] = {
> + {
> + .index = 0,
> + .name = "Composite",
> + .type = V4L2_INPUT_TYPE_CAMERA,
> + .std = TVP514X_STD_ALL,
> + },
> + {
> + .index = 1,
> + .name = "S-Video",
> + .type = V4L2_INPUT_TYPE_CAMERA,
> + .std = TVP514X_STD_ALL,
> + },
> +};
> +
> +/*
> + * this is the route info for connecting each input to decoder
> + * ouput that goes to vpfe. There is a one to one correspondence
> + * with tvp5146_inputs
> + */
> +static struct vpfe_route tvp5146_routes[] = {
> + {
> + .input = INPUT_CVBS_VI2B,
> + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
> + },
> +{
> + .input = INPUT_SVIDEO_VI2C_VI1C,
> + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
> + },
> +};
> +
> +static struct vpfe_subdev_info vpfe_sub_devs[] = {
> +{
> + .module_name = "tvp5146",
> + .grp_id = 0,
> + .num_inputs = ARRAY_SIZE(tvp5146_inputs),
> + .inputs = tvp5146_inputs,
> + .routes = tvp5146_routes,
> + .can_route = 1,
> + .ccdc_if_params = {
> + .if_type = VPFE_BT656,
> + .hdpol = VPFE_PINPOL_POSITIVE,
> + .vdpol = VPFE_PINPOL_POSITIVE,
> + },
> + .board_info = {
> + I2C_BOARD_INFO("tvp5146", 0x5d),
> + .platform_data = &tvp5146_pdata,
> + },
> + }
> +};
> +
> +static struct vpfe_config vpfe_cfg = {
> + .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
> + .sub_devs = vpfe_sub_devs,
> + .card_name = "DM365 EVM",
> + .ccdc = "DM365 ISIF",
> + .num_clocks = 1,
> + .clocks = {"vpss_master"},
> +};
> +
> static struct davinci_mmc_config dm365evm_mmc_config = {
> .get_cd = cpld_mmc_get_cd,
> .get_ro = cpld_mmc_get_ro,
> @@ -461,6 +530,8 @@ static struct davinci_uart_config uart_config __initdata = {
>
> static void __init dm365_evm_map_io(void)
> {
> + /* setup input configuration for VPFE input devices */
> + dm365_set_vpfe_config(&vpfe_cfg);
> dm365_init();
> }
>
> diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
> index f8bac94..aa432d4 100644
> --- a/arch/arm/mach-davinci/dm365.c
> +++ b/arch/arm/mach-davinci/dm365.c
> @@ -904,6 +904,62 @@ void __init dm365_init(void)
> davinci_common_init(&davinci_soc_info_dm365);
> }
>
> +static struct resource dm365_vpss_resources[] = {
> + {
> + /* VPSS ISP5 Base address */
> + .name = "vpss",
> + .start = 0x01c70000,
> + .end = 0x01c70000 + 0xff,
> + .flags = IORESOURCE_MEM,
> + },
> + {
> + /* VPSS CLK Base address */
> + .name = "vpss",
> + .start = 0x01c70200,
> + .end = 0x01c70200 + 0xff,
> + .flags = IORESOURCE_MEM,
> + },
> +};
> +
> +static struct platform_device dm365_vpss_device = {
> + .name = "vpss",
> + .id = -1,
> + .dev.platform_data = "dm365_vpss",
> + .num_resources = ARRAY_SIZE(dm365_vpss_resources),
> + .resource = dm365_vpss_resources,
> +};
> +
> +static struct resource vpfe_resources[] = {
> + {
> + .start = IRQ_VDINT0,
> + .end = IRQ_VDINT0,
> + .flags = IORESOURCE_IRQ,
> + },
> + {
> + .start = IRQ_VDINT1,
> + .end = IRQ_VDINT1,
> + .flags = IORESOURCE_IRQ,
> + },
> + /* ISIF Base address */
> + {
> + .start = 0x01c71000,
> + .end = 0x01c71000 + 0x1ff,
> + .flags = IORESOURCE_MEM,
> + },
> +};
> +
> +static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
> +static struct platform_device vpfe_capture_dev = {
> + .name = CAPTURE_DRV_NAME,
> + .id = -1,
> + .num_resources = ARRAY_SIZE(vpfe_resources),
> + .resource = vpfe_resources,
> + .dev = {
> + .dma_mask = &vpfe_capture_dma_mask,
> + .coherent_dma_mask = DMA_BIT_MASK(32),
> + },
> +};
> +
> static int __init dm365_init_devices(void)
> {
> if (!cpu_is_davinci_dm365())
> @@ -913,6 +969,18 @@ static int __init dm365_init_devices(void)
> platform_device_register(&dm365_edma_device);
> platform_device_register(&dm365_emac_device);
>
> + /*
> + * setup Mux configuration for vpfe input and register
> + * vpfe capture platform device
> + */
> + platform_device_register(&dm365_vpss_device);
> + platform_device_register(&vpfe_capture_dev);
> +
> return 0;
> }
> postcore_initcall(dm365_init_devices);
> +
> +void dm365_set_vpfe_config(struct vpfe_config *cfg)
> +{
> + vpfe_capture_dev.dev.platform_data = cfg;
> +}
> diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
> index 09db434..2fbead2 100644
> --- a/arch/arm/mach-davinci/include/mach/dm365.h
> +++ b/arch/arm/mach-davinci/include/mach/dm365.h
> @@ -15,6 +15,7 @@
>
> #include <linux/platform_device.h>
> #include <mach/hardware.h>
> +#include <media/davinci/vpfe_capture.h>
> #include <mach/emac.h>
>
> #define DM365_EMAC_BASE (0x01D07000)
> @@ -25,5 +26,6 @@
> #define DM365_EMAC_CNTRL_RAM_SIZE (0x2000)
>
> void __init dm365_init(void);
> +void dm365_set_vpfe_config(struct vpfe_config *cfg);
>
> #endif /* __ASM_ARCH_DM365_H */
> --
> 1.6.0.4
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH v1 1/4] DM365 Platform support for VPFE
2009-10-15 23:18 ` [PATCH v1 1/4] DM365 Platform support for VPFE Kevin Hilman
@ 2009-10-16 15:29 ` Karicheri, Muralidharan
2009-10-16 16:35 ` Kevin Hilman
0 siblings, 1 reply; 8+ messages in thread
From: Karicheri, Muralidharan @ 2009-10-16 15:29 UTC (permalink / raw)
To: Kevin Hilman, Sikka, Neil
Cc: davinci-linux-open-source@linux.davincidsp.com,
linux-media@vger.kernel.org
Kevin,
I would like to wait on this one and re-submit a revised patch. There is a plan to use sub device model for ccdc driver. So I will re-submit the ccdc drivers with this change as well as the corresponding platform code.
Murali Karicheri
Software Design Engineer
Texas Instruments Inc.
Germantown, MD 20874
phone: 301-407-9583
email: m-karicheri2@ti.com
>-----Original Message-----
>From: davinci-linux-open-source-bounces@linux.davincidsp.com
>[mailto:davinci-linux-open-source-bounces@linux.davincidsp.com] On Behalf
>Of Kevin Hilman
>Sent: Thursday, October 15, 2009 7:18 PM
>To: Sikka, Neil
>Cc: davinci-linux-open-source@linux.davincidsp.com; linux-
>media@vger.kernel.org
>Subject: Re: [PATCH v1 1/4] DM365 Platform support for VPFE
>
>neilsikka@ti.com writes:
>
>> From: Neil Sikka <neilsikka@ti.com>
>>
>> This has platform and board setup changes to support the vpfe capture
>> driver for DM365 EVMs.
>>
>> Reviewed-by: Muralidharan Karicheri <m-karicheri2@ti.com>
>> Mandatory-Reviewer: Hans Verkuil <hverkuil@xs4all.nl>
>> Mandatory-Reviewer: Kevin Hilman <khilman@deeprootsystems.com>
>> Signed-off-by: Neil Sikka <neilsikka@ti.com>
>
>Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
>
>for this patch, but the rest of the series needs to be reviewed by linux-
>media folks.
>
>Kevin
>
>
>> ---
>> Applies to Kevin Hilman's linux-davinci repository
>> arch/arm/mach-davinci/board-dm365-evm.c | 71
>++++++++++++++++++++++++++++
>> arch/arm/mach-davinci/dm365.c | 68
>++++++++++++++++++++++++++
>> arch/arm/mach-davinci/include/mach/dm365.h | 2 +
>> 3 files changed, 141 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-
>davinci/board-dm365-evm.c
>> index f6adf79..757ad13 100644
>> --- a/arch/arm/mach-davinci/board-dm365-evm.c
>> +++ b/arch/arm/mach-davinci/board-dm365-evm.c
>> @@ -38,6 +38,8 @@
>> #include <mach/common.h>
>> #include <mach/mmc.h>
>> #include <mach/nand.h>
>> +#include <linux/videodev2.h>
>> +#include <media/tvp514x.h>
>>
>>
>> static inline int have_imager(void)
>> @@ -98,6 +100,11 @@ static inline int have_tvp7002(void)
>>
>> static void __iomem *cpld;
>>
>> +static struct tvp514x_platform_data tvp5146_pdata = {
>> + .clk_polarity = 0,
>> + .hs_polarity = 1,
>> + .vs_polarity = 1
>> +};
>>
>> /* NOTE: this is geared for the standard config, with a socketed
>> * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
>> @@ -210,6 +217,68 @@ static int cpld_mmc_get_ro(int module)
>> return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
>> }
>>
>> +#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
>> +/* Inputs available at the TVP5146 */
>> +static struct v4l2_input tvp5146_inputs[] = {
>> + {
>> + .index = 0,
>> + .name = "Composite",
>> + .type = V4L2_INPUT_TYPE_CAMERA,
>> + .std = TVP514X_STD_ALL,
>> + },
>> + {
>> + .index = 1,
>> + .name = "S-Video",
>> + .type = V4L2_INPUT_TYPE_CAMERA,
>> + .std = TVP514X_STD_ALL,
>> + },
>> +};
>> +
>> +/*
>> + * this is the route info for connecting each input to decoder
>> + * ouput that goes to vpfe. There is a one to one correspondence
>> + * with tvp5146_inputs
>> + */
>> +static struct vpfe_route tvp5146_routes[] = {
>> + {
>> + .input = INPUT_CVBS_VI2B,
>> + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
>> + },
>> +{
>> + .input = INPUT_SVIDEO_VI2C_VI1C,
>> + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
>> + },
>> +};
>> +
>> +static struct vpfe_subdev_info vpfe_sub_devs[] = {
>> +{
>> + .module_name = "tvp5146",
>> + .grp_id = 0,
>> + .num_inputs = ARRAY_SIZE(tvp5146_inputs),
>> + .inputs = tvp5146_inputs,
>> + .routes = tvp5146_routes,
>> + .can_route = 1,
>> + .ccdc_if_params = {
>> + .if_type = VPFE_BT656,
>> + .hdpol = VPFE_PINPOL_POSITIVE,
>> + .vdpol = VPFE_PINPOL_POSITIVE,
>> + },
>> + .board_info = {
>> + I2C_BOARD_INFO("tvp5146", 0x5d),
>> + .platform_data = &tvp5146_pdata,
>> + },
>> + }
>> +};
>> +
>> +static struct vpfe_config vpfe_cfg = {
>> + .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
>> + .sub_devs = vpfe_sub_devs,
>> + .card_name = "DM365 EVM",
>> + .ccdc = "DM365 ISIF",
>> + .num_clocks = 1,
>> + .clocks = {"vpss_master"},
>> +};
>> +
>> static struct davinci_mmc_config dm365evm_mmc_config = {
>> .get_cd = cpld_mmc_get_cd,
>> .get_ro = cpld_mmc_get_ro,
>> @@ -461,6 +530,8 @@ static struct davinci_uart_config uart_config
>__initdata = {
>>
>> static void __init dm365_evm_map_io(void)
>> {
>> + /* setup input configuration for VPFE input devices */
>> + dm365_set_vpfe_config(&vpfe_cfg);
>> dm365_init();
>> }
>>
>> diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-
>davinci/dm365.c
>> index f8bac94..aa432d4 100644
>> --- a/arch/arm/mach-davinci/dm365.c
>> +++ b/arch/arm/mach-davinci/dm365.c
>> @@ -904,6 +904,62 @@ void __init dm365_init(void)
>> davinci_common_init(&davinci_soc_info_dm365);
>> }
>>
>> +static struct resource dm365_vpss_resources[] = {
>> + {
>> + /* VPSS ISP5 Base address */
>> + .name = "vpss",
>> + .start = 0x01c70000,
>> + .end = 0x01c70000 + 0xff,
>> + .flags = IORESOURCE_MEM,
>> + },
>> + {
>> + /* VPSS CLK Base address */
>> + .name = "vpss",
>> + .start = 0x01c70200,
>> + .end = 0x01c70200 + 0xff,
>> + .flags = IORESOURCE_MEM,
>> + },
>> +};
>> +
>> +static struct platform_device dm365_vpss_device = {
>> + .name = "vpss",
>> + .id = -1,
>> + .dev.platform_data = "dm365_vpss",
>> + .num_resources = ARRAY_SIZE(dm365_vpss_resources),
>> + .resource = dm365_vpss_resources,
>> +};
>> +
>> +static struct resource vpfe_resources[] = {
>> + {
>> + .start = IRQ_VDINT0,
>> + .end = IRQ_VDINT0,
>> + .flags = IORESOURCE_IRQ,
>> + },
>> + {
>> + .start = IRQ_VDINT1,
>> + .end = IRQ_VDINT1,
>> + .flags = IORESOURCE_IRQ,
>> + },
>> + /* ISIF Base address */
>> + {
>> + .start = 0x01c71000,
>> + .end = 0x01c71000 + 0x1ff,
>> + .flags = IORESOURCE_MEM,
>> + },
>> +};
>> +
>> +static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
>> +static struct platform_device vpfe_capture_dev = {
>> + .name = CAPTURE_DRV_NAME,
>> + .id = -1,
>> + .num_resources = ARRAY_SIZE(vpfe_resources),
>> + .resource = vpfe_resources,
>> + .dev = {
>> + .dma_mask = &vpfe_capture_dma_mask,
>> + .coherent_dma_mask = DMA_BIT_MASK(32),
>> + },
>> +};
>> +
>> static int __init dm365_init_devices(void)
>> {
>> if (!cpu_is_davinci_dm365())
>> @@ -913,6 +969,18 @@ static int __init dm365_init_devices(void)
>> platform_device_register(&dm365_edma_device);
>> platform_device_register(&dm365_emac_device);
>>
>> + /*
>> + * setup Mux configuration for vpfe input and register
>> + * vpfe capture platform device
>> + */
>> + platform_device_register(&dm365_vpss_device);
>> + platform_device_register(&vpfe_capture_dev);
>> +
>> return 0;
>> }
>> postcore_initcall(dm365_init_devices);
>> +
>> +void dm365_set_vpfe_config(struct vpfe_config *cfg)
>> +{
>> + vpfe_capture_dev.dev.platform_data = cfg;
>> +}
>> diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-
>davinci/include/mach/dm365.h
>> index 09db434..2fbead2 100644
>> --- a/arch/arm/mach-davinci/include/mach/dm365.h
>> +++ b/arch/arm/mach-davinci/include/mach/dm365.h
>> @@ -15,6 +15,7 @@
>>
>> #include <linux/platform_device.h>
>> #include <mach/hardware.h>
>> +#include <media/davinci/vpfe_capture.h>
>> #include <mach/emac.h>
>>
>> #define DM365_EMAC_BASE (0x01D07000)
>> @@ -25,5 +26,6 @@
>> #define DM365_EMAC_CNTRL_RAM_SIZE (0x2000)
>>
>> void __init dm365_init(void);
>> +void dm365_set_vpfe_config(struct vpfe_config *cfg);
>>
>> #endif /* __ASM_ARCH_DM365_H */
>> --
>> 1.6.0.4
>
>_______________________________________________
>Davinci-linux-open-source mailing list
>Davinci-linux-open-source@linux.davincidsp.com
>http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v1 1/4] DM365 Platform support for VPFE
2009-10-16 15:29 ` Karicheri, Muralidharan
@ 2009-10-16 16:35 ` Kevin Hilman
0 siblings, 0 replies; 8+ messages in thread
From: Kevin Hilman @ 2009-10-16 16:35 UTC (permalink / raw)
To: Karicheri, Muralidharan
Cc: Sikka, Neil, davinci-linux-open-source@linux.davincidsp.com,
linux-media@vger.kernel.org
"Karicheri, Muralidharan" <m-karicheri2@ti.com> writes:
> I would like to wait on this one and re-submit a revised
> patch. There is a plan to use sub device model for ccdc driver. So I
> will re-submit the ccdc drivers with this change as well as the
> corresponding platform code.
Murali,
OK, thanks for the update, I'll drop from my queue and wait for
updated version.
Kevin
>>-----Original Message-----
>>From: davinci-linux-open-source-bounces@linux.davincidsp.com
>>[mailto:davinci-linux-open-source-bounces@linux.davincidsp.com] On Behalf
>>Of Kevin Hilman
>>Sent: Thursday, October 15, 2009 7:18 PM
>>To: Sikka, Neil
>>Cc: davinci-linux-open-source@linux.davincidsp.com; linux-
>>media@vger.kernel.org
>>Subject: Re: [PATCH v1 1/4] DM365 Platform support for VPFE
>>
>>neilsikka@ti.com writes:
>>
>>> From: Neil Sikka <neilsikka@ti.com>
>>>
>>> This has platform and board setup changes to support the vpfe capture
>>> driver for DM365 EVMs.
>>>
>>> Reviewed-by: Muralidharan Karicheri <m-karicheri2@ti.com>
>>> Mandatory-Reviewer: Hans Verkuil <hverkuil@xs4all.nl>
>>> Mandatory-Reviewer: Kevin Hilman <khilman@deeprootsystems.com>
>>> Signed-off-by: Neil Sikka <neilsikka@ti.com>
>>
>>Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
>>
>>for this patch, but the rest of the series needs to be reviewed by linux-
>>media folks.
>>
>>Kevin
>>
>>
>>> ---
>>> Applies to Kevin Hilman's linux-davinci repository
>>> arch/arm/mach-davinci/board-dm365-evm.c | 71
>>++++++++++++++++++++++++++++
>>> arch/arm/mach-davinci/dm365.c | 68
>>++++++++++++++++++++++++++
>>> arch/arm/mach-davinci/include/mach/dm365.h | 2 +
>>> 3 files changed, 141 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-
>>davinci/board-dm365-evm.c
>>> index f6adf79..757ad13 100644
>>> --- a/arch/arm/mach-davinci/board-dm365-evm.c
>>> +++ b/arch/arm/mach-davinci/board-dm365-evm.c
>>> @@ -38,6 +38,8 @@
>>> #include <mach/common.h>
>>> #include <mach/mmc.h>
>>> #include <mach/nand.h>
>>> +#include <linux/videodev2.h>
>>> +#include <media/tvp514x.h>
>>>
>>>
>>> static inline int have_imager(void)
>>> @@ -98,6 +100,11 @@ static inline int have_tvp7002(void)
>>>
>>> static void __iomem *cpld;
>>>
>>> +static struct tvp514x_platform_data tvp5146_pdata = {
>>> + .clk_polarity = 0,
>>> + .hs_polarity = 1,
>>> + .vs_polarity = 1
>>> +};
>>>
>>> /* NOTE: this is geared for the standard config, with a socketed
>>> * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
>>> @@ -210,6 +217,68 @@ static int cpld_mmc_get_ro(int module)
>>> return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
>>> }
>>>
>>> +#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
>>> +/* Inputs available at the TVP5146 */
>>> +static struct v4l2_input tvp5146_inputs[] = {
>>> + {
>>> + .index = 0,
>>> + .name = "Composite",
>>> + .type = V4L2_INPUT_TYPE_CAMERA,
>>> + .std = TVP514X_STD_ALL,
>>> + },
>>> + {
>>> + .index = 1,
>>> + .name = "S-Video",
>>> + .type = V4L2_INPUT_TYPE_CAMERA,
>>> + .std = TVP514X_STD_ALL,
>>> + },
>>> +};
>>> +
>>> +/*
>>> + * this is the route info for connecting each input to decoder
>>> + * ouput that goes to vpfe. There is a one to one correspondence
>>> + * with tvp5146_inputs
>>> + */
>>> +static struct vpfe_route tvp5146_routes[] = {
>>> + {
>>> + .input = INPUT_CVBS_VI2B,
>>> + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
>>> + },
>>> +{
>>> + .input = INPUT_SVIDEO_VI2C_VI1C,
>>> + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
>>> + },
>>> +};
>>> +
>>> +static struct vpfe_subdev_info vpfe_sub_devs[] = {
>>> +{
>>> + .module_name = "tvp5146",
>>> + .grp_id = 0,
>>> + .num_inputs = ARRAY_SIZE(tvp5146_inputs),
>>> + .inputs = tvp5146_inputs,
>>> + .routes = tvp5146_routes,
>>> + .can_route = 1,
>>> + .ccdc_if_params = {
>>> + .if_type = VPFE_BT656,
>>> + .hdpol = VPFE_PINPOL_POSITIVE,
>>> + .vdpol = VPFE_PINPOL_POSITIVE,
>>> + },
>>> + .board_info = {
>>> + I2C_BOARD_INFO("tvp5146", 0x5d),
>>> + .platform_data = &tvp5146_pdata,
>>> + },
>>> + }
>>> +};
>>> +
>>> +static struct vpfe_config vpfe_cfg = {
>>> + .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
>>> + .sub_devs = vpfe_sub_devs,
>>> + .card_name = "DM365 EVM",
>>> + .ccdc = "DM365 ISIF",
>>> + .num_clocks = 1,
>>> + .clocks = {"vpss_master"},
>>> +};
>>> +
>>> static struct davinci_mmc_config dm365evm_mmc_config = {
>>> .get_cd = cpld_mmc_get_cd,
>>> .get_ro = cpld_mmc_get_ro,
>>> @@ -461,6 +530,8 @@ static struct davinci_uart_config uart_config
>>__initdata = {
>>>
>>> static void __init dm365_evm_map_io(void)
>>> {
>>> + /* setup input configuration for VPFE input devices */
>>> + dm365_set_vpfe_config(&vpfe_cfg);
>>> dm365_init();
>>> }
>>>
>>> diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-
>>davinci/dm365.c
>>> index f8bac94..aa432d4 100644
>>> --- a/arch/arm/mach-davinci/dm365.c
>>> +++ b/arch/arm/mach-davinci/dm365.c
>>> @@ -904,6 +904,62 @@ void __init dm365_init(void)
>>> davinci_common_init(&davinci_soc_info_dm365);
>>> }
>>>
>>> +static struct resource dm365_vpss_resources[] = {
>>> + {
>>> + /* VPSS ISP5 Base address */
>>> + .name = "vpss",
>>> + .start = 0x01c70000,
>>> + .end = 0x01c70000 + 0xff,
>>> + .flags = IORESOURCE_MEM,
>>> + },
>>> + {
>>> + /* VPSS CLK Base address */
>>> + .name = "vpss",
>>> + .start = 0x01c70200,
>>> + .end = 0x01c70200 + 0xff,
>>> + .flags = IORESOURCE_MEM,
>>> + },
>>> +};
>>> +
>>> +static struct platform_device dm365_vpss_device = {
>>> + .name = "vpss",
>>> + .id = -1,
>>> + .dev.platform_data = "dm365_vpss",
>>> + .num_resources = ARRAY_SIZE(dm365_vpss_resources),
>>> + .resource = dm365_vpss_resources,
>>> +};
>>> +
>>> +static struct resource vpfe_resources[] = {
>>> + {
>>> + .start = IRQ_VDINT0,
>>> + .end = IRQ_VDINT0,
>>> + .flags = IORESOURCE_IRQ,
>>> + },
>>> + {
>>> + .start = IRQ_VDINT1,
>>> + .end = IRQ_VDINT1,
>>> + .flags = IORESOURCE_IRQ,
>>> + },
>>> + /* ISIF Base address */
>>> + {
>>> + .start = 0x01c71000,
>>> + .end = 0x01c71000 + 0x1ff,
>>> + .flags = IORESOURCE_MEM,
>>> + },
>>> +};
>>> +
>>> +static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
>>> +static struct platform_device vpfe_capture_dev = {
>>> + .name = CAPTURE_DRV_NAME,
>>> + .id = -1,
>>> + .num_resources = ARRAY_SIZE(vpfe_resources),
>>> + .resource = vpfe_resources,
>>> + .dev = {
>>> + .dma_mask = &vpfe_capture_dma_mask,
>>> + .coherent_dma_mask = DMA_BIT_MASK(32),
>>> + },
>>> +};
>>> +
>>> static int __init dm365_init_devices(void)
>>> {
>>> if (!cpu_is_davinci_dm365())
>>> @@ -913,6 +969,18 @@ static int __init dm365_init_devices(void)
>>> platform_device_register(&dm365_edma_device);
>>> platform_device_register(&dm365_emac_device);
>>>
>>> + /*
>>> + * setup Mux configuration for vpfe input and register
>>> + * vpfe capture platform device
>>> + */
>>> + platform_device_register(&dm365_vpss_device);
>>> + platform_device_register(&vpfe_capture_dev);
>>> +
>>> return 0;
>>> }
>>> postcore_initcall(dm365_init_devices);
>>> +
>>> +void dm365_set_vpfe_config(struct vpfe_config *cfg)
>>> +{
>>> + vpfe_capture_dev.dev.platform_data = cfg;
>>> +}
>>> diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-
>>davinci/include/mach/dm365.h
>>> index 09db434..2fbead2 100644
>>> --- a/arch/arm/mach-davinci/include/mach/dm365.h
>>> +++ b/arch/arm/mach-davinci/include/mach/dm365.h
>>> @@ -15,6 +15,7 @@
>>>
>>> #include <linux/platform_device.h>
>>> #include <mach/hardware.h>
>>> +#include <media/davinci/vpfe_capture.h>
>>> #include <mach/emac.h>
>>>
>>> #define DM365_EMAC_BASE (0x01D07000)
>>> @@ -25,5 +26,6 @@
>>> #define DM365_EMAC_CNTRL_RAM_SIZE (0x2000)
>>>
>>> void __init dm365_init(void);
>>> +void dm365_set_vpfe_config(struct vpfe_config *cfg);
>>>
>>> #endif /* __ASM_ARCH_DM365_H */
>>> --
>>> 1.6.0.4
>>
>>_______________________________________________
>>Davinci-linux-open-source mailing list
>>Davinci-linux-open-source@linux.davincidsp.com
>>http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2009-10-16 16:35 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2009-08-17 20:05 [PATCH v1 0/4] Adding capture support for DM365 device neilsikka
2009-08-17 20:05 ` [PATCH v1 1/4] DM365 Platform support for VPFE neilsikka
2009-08-17 20:05 ` [PATCH v1 2/4] DM365 VPSS support neilsikka
2009-08-17 20:05 ` [PATCH v1 3/4] CCDC support on DM365 neilsikka
2009-08-17 20:05 ` [PATCH v1 4/4] Build system support for DM365 CCDC neilsikka
2009-10-15 23:18 ` [PATCH v1 1/4] DM365 Platform support for VPFE Kevin Hilman
2009-10-16 15:29 ` Karicheri, Muralidharan
2009-10-16 16:35 ` Kevin Hilman
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