From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5CFC33A003; Thu, 20 Nov 2025 13:44:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763646272; cv=none; b=WEaKEH+6hikDDEuObxEgQdhUtJfnc9x8fcFDuwxsEaishlZyfHXrT1qXpLe1gJ2/cKNeOp2bx9sUrlA/cJUzep560IzeF3MOh+OL6On5JBSyNeOC+Ac356OTX+DFzHlN3jeQKeFqAlg2akgfUq04IWI0k2PI0U7isYOQcr5MAIY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763646272; c=relaxed/simple; bh=CLQfYe5K8BnIGRpXDic6QZBVupxIpc6StQw66vm6qGY=; h=Message-ID:Date:MIME-Version:Subject:To:References:From: In-Reply-To:Content-Type; b=aa6qxWwxPb7dkRuNhOqFNsXJn1BzyPlZ5/9OrvoUYOKub0mdHS48H9j+wbtj5aWzQXmT9Opg60HdcwFowLezNJYYX6s3zzliN41xtOSU9lc1mX092Dyct9kDJpf+3+Cf8nx75/qjuKF+ZyJ9yEWCQEORWImchUT37oYpebJKfVE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=msNtPb/b; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="msNtPb/b" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 08CA9C4CEF1; Thu, 20 Nov 2025 13:44:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763646272; bh=CLQfYe5K8BnIGRpXDic6QZBVupxIpc6StQw66vm6qGY=; h=Date:Subject:To:References:From:In-Reply-To:From; b=msNtPb/bV/K2drAC1HLFyLmgEV+FsOshiWpAdYDThL4QVHbXZT/u2LNxalWg4hEfe NuunQ2+CsWXr2zBFUuoeKHF9YlzYMD6uKegjD3QHGjxiitXrWC5alaguY2i2N1MK/e axpcftm5J0aVOw/kofzXnpLrwEiem9txWgCRNZ6vyIwHDGhSCt07EfxFgEsrU/4up9 UwhfSGLxTKZ4GjXMNBuQMdUuUyS5RFqMD48PFTK9Sah4F5NtIyK4nmzSKqT7Ltz52c 231U4cix5FKkxjtpgpKBG0HBA174cju4xdFOAuZmta/k/EP2TYHr6fXru5suFg71uX C874fjmdEPzhA== Message-ID: <9ecd6482-5ef9-479d-a0ea-5dc06e3b9ffb@kernel.org> Date: Thu, 20 Nov 2025 14:44:28 +0100 Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/4] media: dt-bindings: adi,adv7180: add VPP and CSI register maps To: Michael Tretter , Lars-Peter Clausen , =?UTF-8?Q?Niklas_S=C3=B6derlund?= , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-media@vger.kernel.org, devicetree@vger.kernel.org, kernel@pengutronix.de References: <20251119-b4-adv7180-vpp-sub-device-v2-0-86a7790b63ab@pengutronix.de> <20251119-b4-adv7180-vpp-sub-device-v2-1-86a7790b63ab@pengutronix.de> <20251120-calm-invisible-bullmastiff-ceaf71@kuoka> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 20/11/2025 13:01, Michael Tretter wrote: > On Thu, 20 Nov 2025 10:05:43 +0100, Krzysztof Kozlowski wrote: >> On 20/11/2025 09:53, Michael Tretter wrote: >>> On Thu, 20 Nov 2025 09:04:48 +0100, Krzysztof Kozlowski wrote: >>>> On Wed, Nov 19, 2025 at 05:25:51PM +0100, Michael Tretter wrote: >>>>> diff --git a/Documentation/devicetree/bindings/media/i2c/adi,adv7180.yaml b/Documentation/devicetree/bindings/media/i2c/adi,adv7180.yaml >>>>> index dee8ce7cb7ba..dbbbe76291bc 100644 >>>>> --- a/Documentation/devicetree/bindings/media/i2c/adi,adv7180.yaml >>>>> +++ b/Documentation/devicetree/bindings/media/i2c/adi,adv7180.yaml >>>>> @@ -30,7 +30,27 @@ properties: >>>>> - adi,adv7282-m >>>>> >>>>> reg: >>>>> - maxItems: 1 >>>>> + minItems: 1 >>>>> + items: >>>>> + - description: main register map >>>>> + - description: CSI register map >>>>> + - description: VPP register map >>>>> + description: >>>>> + The ADV7180 family may have up to three register maps. All chips have >>>>> + the main register map. The availability of the CSI and VPP register maps >>>>> + depends on the chip variant. >>>>> + >>>>> + The addresses of the CSI and VPP register maps are programmable by >>>>> + software. They depend on the board layout and other devices on the I2C >>>>> + bus and are determined by the hardware designer to avoid address >>>>> + conflicts on the I2C bus. >>>>> + >>>>> + reg-names: >>>>> + minItems: 1 >>>>> + items: >>>>> + - const: main >>>>> + - enum: [ csi, vpp ] >>>>> + - enum: [ csi, vpp ] >>>> >>>> Last entry must be: >>>> >>>> const: vpp >>>> >>>> We do not allow flexible order... but the problem is that your if:then: >>>> does not match above at all. You do not have three items anywhere. >>> >>> I'm not entirely sure, if I correctly understand that comment. >>> >>> The adi,adv7280-m and adi,adv7282-m have all three items and don't need >>> an if:then:. Do I have explicitly define the binding with three items, >>> too? >> >> Which comment? That third item cannot be csi? What is odd here? >> >> >>> >>> The chip has the following variants: >>> >>> adi,adv7180: main >>> adi,adv7180cp: main >>> adi,adv7180st: main >>> adi,adv7182: main >>> adi,adv7280: main, vpp >>> adi,adv7280-m: main, csi, vpp >>> adi,adv7281: main, csi >>> adi,adv7281-m: main, csi >>> adi,adv7281-ma: main, csi >>> adi,adv7282: main, vpp >>> adi,adv7282-m: main, csi, vpp >> >> So where is csi as third item? >> >> Anyway, you also miss minItems in your if:then: cases. > > The minItems in the if:then: cases would be the same as in the top level > definition. Do I have to override the minItems if it's the same? Yes, you need to make it explicit. All constraints, except min=maxItems, which you imply here, must be explicit. > >> >>> >>> If I make the last entry (vpp) const, I allow exactly these variants. >>> >>> For the adi,adv7280-m compatible, the following combinations would be >>> valid or invalid: >>> >>> adi,adv7280-m: main >>> >>> is valid, because only main is mandatory. For csi and vpp, the default >>> addresses are used. >>> >>> adi,adv7280-m: main, vpp >>> >>> is valid, because the second entry may be vpp. For csi, the default >>> address is used. >>> >>> adi,adv7280-m: main, vpp, csi >>> >>> is invalid, because the entries must be in the defined order, and >>> flexible order is not possible. >>> >>> Is this correct and matches the binding definition? >> >> It does not match your code. > > If I change the last entry to > > - const: csi > > to disallow vpp as a third item (which is compliant to the example), the > binding is fine. Correct? Probably, lost context, because I asked you to do that but it felt like you keep discussing. So if you implement reviewer's suggestion, it is enough to say "ack" or "ok". Best regards, Krzysztof