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Tue, 24 Mar 2026 08:58:02 -0700 (PDT) X-Received: by 2002:a05:6214:570d:b0:899:f5a4:8110 with SMTP id 6a1803df08f44-89cc4adc756mr1981856d6.56.1774367882087; Tue, 24 Mar 2026 08:58:02 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20260323125824.211615-1-loic.poulain@oss.qualcomm.com> <20260323125824.211615-3-loic.poulain@oss.qualcomm.com> <1ba54ec0-be51-4694-a79b-f272e76303d2@kernel.org> <12194cc0-0960-486c-be7e-1a22d95de340@kernel.org> In-Reply-To: <12194cc0-0960-486c-be7e-1a22d95de340@kernel.org> From: Loic Poulain Date: Tue, 24 Mar 2026 16:57:51 +0100 X-Gm-Features: AaiRm52QkkxQCqRqr-Jt62eDyvDcyXaIOYwIWRquF6V_Pbmf84Rb_fN-zDuHgQA Message-ID: Subject: Re: [RFC PATCH 2/3] media: qcom: camss: Add CAMSS Offline Processing Engine driver To: "Bryan O'Donoghue" Cc: vladimir.zapolskiy@linaro.org, laurent.pinchart@ideasonboard.com, kieran.bingham@ideasonboard.com, robh@kernel.org, krzk+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, johannes.goede@oss.qualcomm.com, mchehab@kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: IKf1APEf_YfxffG3aw1_JNgWVNhpsJH6 X-Authority-Analysis: v=2.4 cv=Nc3rFmD4 c=1 sm=1 tr=0 ts=69c2b48b cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=VwQbUJbxAAAA:8 a=lx2B71hQoDIPyAvjx6AA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-GUID: IKf1APEf_YfxffG3aw1_JNgWVNhpsJH6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI0MDEyMyBTYWx0ZWRfXyIwfe0JvP3QL JKigUXKFSaLilHuymTDJpIJX63e8HR4oU87Jm+uU7h647V5i2z3FTIESEtsQ1e/N+RHQLUZApAy /THuRs4k7SeJ/tHmq8CctFhc5XIoA6S6S/jmbJu07ihi7BKUGkOMq7Yv87V9YyUCw7ifNI06wLR MLjLlcwQoA4tqUNIE2OJJD0QFb0Yn0z5Qj6dPjFO9A7HRWrBc//Tvos7Yg2vwN9F96mKVUXv57p ekQjwNd4LL3t/NQH5f+j5WV9poCBfS+libpBO0RcOiZJpdX8F6IounwetcXz7Hc6RNKZWxZm9y6 eLPiDOa1uxWdHCC+2BpzRbfRqBojW0hxTRrXIRF5YmnvhnN3hL3nUkjlqbCdBXWsG1QmKWVIPyW rHavGcpZma5x0FGhzpwYvpJm6wSIta+5BaHmDZUCuXWNEXfr4Qnonc/1wWQB0NOdtMQcqT/pyph 5OlMwytoqPHJek2iMGg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-24_03,2026-03-23_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 spamscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603240123 Hi Bryan, On Tue, Mar 24, 2026 at 12:00=E2=80=AFPM Bryan O'Donoghue = wrote: > > On 23/03/2026 15:31, Loic Poulain wrote: > >>> + > >>> +static void ope_prog_bayer2rgb(struct ope_dev *ope) > >>> +{ > >>> + /* Fixed Settings */ > >>> + ope_write_pp(ope, 0x860, 0x4001); > >>> + ope_write_pp(ope, 0x868, 128); > >>> + ope_write_pp(ope, 0x86c, 128 << 20); > >>> + ope_write_pp(ope, 0x870, 102); > >> What are the magic numbers about ? Please define bit-fields and offset= s. > > There are some registers I can't disclose today, which have to be > > configured with working values, > > Similarly to some sensor configuration in media/i2c. > > Not really the same thing, all of the offsets in upstream CAMSS and its > CLC are documented. Sensor values are typically upstreamed by people who > don't control the documentation, that is not the case with Qcom > submitting this code upstream now. > > Are you guys doing an upstream implementation or not ? Yes, but some configuration will be static and non-parametrable, I will check if we can at least document the layout. > > >> Parameters passed in from user-space/libcamera and then translated to > >> registers etc. > > The above fixed settings will not be part of the initial parameters. > > > >>> +} > >>> + > >>> +static void ope_prog_wb(struct ope_dev *ope) > >>> +{ > >>> + /* Default white balance config */ > >>> + u32 g_gain =3D OPE_WB(1, 1); > >>> + u32 b_gain =3D OPE_WB(3, 2); > >>> + u32 r_gain =3D OPE_WB(3, 2); > >>> + > >>> + ope_write_pp(ope, OPE_PP_CLC_WB_GAIN_WB_CFG(0), g_gain); > >>> + ope_write_pp(ope, OPE_PP_CLC_WB_GAIN_WB_CFG(1), b_gain); > >>> + ope_write_pp(ope, OPE_PP_CLC_WB_GAIN_WB_CFG(2), r_gain); > >>> + > >>> + ope_write_pp(ope, OPE_PP_CLC_WB_GAIN_MODULE_CFG, OPE_PP_CLC_WB_= GAIN_MODULE_CFG_EN); > >>> +} > >> Fixed gains will have to come from real data. > > These gains will indeed need to be configurable, most likely via ISP > > parameters, here, they have been adjusted based on colorbar test > > pattern from imx219 sensors but also tested with real capture. > > > >>> + > >>> +static void ope_prog_stripe(struct ope_ctx *ctx, struct ope_stripe *= stripe) > >>> +{ > >>> + struct ope_dev *ope =3D ctx->ope; > >>> + int i; > >>> + > >>> + dev_dbg(ope->dev, "Context %p - Programming S%u\n", ctx, ope_st= ripe_index(ctx, stripe)); > >>> + > >>> + /* Fetch Engine */ > >>> + ope_write_rd(ope, OPE_BUS_RD_CLIENT_0_UNPACK_CFG_0, stripe->src= .format); > >>> + ope_write_rd(ope, OPE_BUS_RD_CLIENT_0_RD_BUFFER_SIZE, > >>> + (stripe->src.width << 16) + stripe->src.height); > >>> + ope_write_rd(ope, OPE_BUS_RD_CLIENT_0_ADDR_IMAGE, stripe->src.a= ddr); > >>> + ope_write_rd(ope, OPE_BUS_RD_CLIENT_0_RD_STRIDE, stripe->src.st= ride); > >>> + ope_write_rd(ope, OPE_BUS_RD_CLIENT_0_CCIF_META_DATA, > >>> + FIELD_PREP(OPE_BUS_RD_CLIENT_0_CCIF_MD_PIX_PATTERN= , stripe->src.pattern)); > >>> + ope_write_rd(ope, OPE_BUS_RD_CLIENT_0_CORE_CFG, OPE_BUS_RD_CLIE= NT_0_CORE_CFG_EN); > >>> + > >>> + /* Write Engines */ > >>> + for (i =3D 0; i < OPE_WR_CLIENT_MAX; i++) { > >>> + if (!stripe->dst[i].enabled) { > >>> + ope_write_wr(ope, OPE_BUS_WR_CLIENT_CFG(i), 0); > >>> + continue; > >>> + } > >>> + > >>> + ope_write_wr(ope, OPE_BUS_WR_CLIENT_ADDR_IMAGE(i), stri= pe->dst[i].addr); > >>> + ope_write_wr(ope, OPE_BUS_WR_CLIENT_IMAGE_CFG_0(i), > >>> + (stripe->dst[i].height << 16) + stripe->ds= t[i].width); > >>> + ope_write_wr(ope, OPE_BUS_WR_CLIENT_IMAGE_CFG_1(i), str= ipe->dst[i].x_init); > >>> + ope_write_wr(ope, OPE_BUS_WR_CLIENT_IMAGE_CFG_2(i), str= ipe->dst[i].stride); > >>> + ope_write_wr(ope, OPE_BUS_WR_CLIENT_PACKER_CFG(i), stri= pe->dst[i].format); > >>> + ope_write_wr(ope, OPE_BUS_WR_CLIENT_CFG(i), > >>> + OPE_BUS_WR_CLIENT_CFG_EN + OPE_BUS_WR_CLIE= NT_CFG_AUTORECOVER); > >>> + } > >>> + > >>> + /* Downscalers */ > >>> + for (i =3D 0; i < OPE_DS_MAX; i++) { > >>> + struct ope_dsc_config *dsc =3D &stripe->dsc[i]; > >>> + u32 base =3D ope_ds_base[i]; > >>> + u32 cfg =3D 0; > >>> + > >>> + if (dsc->input_width !=3D dsc->output_width) { > >>> + dsc->phase_step_h |=3D DS_RESOLUTION(dsc->input= _width, > >>> + dsc->output_= width) << 30; > >>> + cfg |=3D OPE_PP_CLC_DOWNSCALE_MN_DS_CFG_H_SCALE= _EN; > >>> + } > >>> + > >>> + if (dsc->input_height !=3D dsc->output_height) { > >>> + dsc->phase_step_v |=3D DS_RESOLUTION(dsc->input= _height, > >>> + dsc->output_= height) << 30; > >>> + cfg |=3D OPE_PP_CLC_DOWNSCALE_MN_DS_CFG_V_SCALE= _EN; > >>> + } > >>> + > >>> + ope_write_pp(ope, OPE_PP_CLC_DOWNSCALE_MN_DS_CFG(base),= cfg); > >>> + ope_write_pp(ope, OPE_PP_CLC_DOWNSCALE_MN_DS_IMAGE_SIZE= _CFG(base), > >>> + ((dsc->input_width - 1) << 16) + dsc->inpu= t_height - 1); > >>> + ope_write_pp(ope, OPE_PP_CLC_DOWNSCALE_MN_DS_MN_H_CFG(b= ase), dsc->phase_step_h); > >>> + ope_write_pp(ope, OPE_PP_CLC_DOWNSCALE_MN_DS_MN_V_CFG(b= ase), dsc->phase_step_v); > >>> + ope_write_pp(ope, OPE_PP_CLC_DOWNSCALE_MN_CFG(base), > >>> + cfg ? OPE_PP_CLC_DOWNSCALE_MN_CFG_EN : 0); > >>> + } > >>> +} > >> So - this is where the CDM should be used - so that you don't have to = do > >> all of these MMIO writes inside of your ISR. > > Indeed, and that also the reason stripes are computed ahead of time, > > so that they can be further 'queued' in a CDM. > > > >> Is that and additional step after the RFC ? > > The current implementation (without CDM) already provides good results > > and performance, so CDM can be viewed as a future enhancement. > > That's true but then the number of MMIO writes per ISR is pretty small > right now. You have about 50 writes here. Right, it will increase significantly. The idea was to start with a version that omits CDM so that we can focus on the other functional aspects of the ISP for now. > > > As far as I understand, CDM could also be implemented in a generic way > > within CAMSS, since other CAMSS blocks make use of CDM as well. > > This is something we should discuss further. > My concern is even conservatively if each module adds another 10 ? > writes by the time we get to denoising, sharpening, lens shade > correction, those writes could easily look more like 100. > > What user-space should submit is well documented data-structures which > then get translated into CDM buffers by the OPE and IFE for the various > bits of the pipeline. Yes it will. Regards, Loic