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Mon, 23 Mar 2026 09:31:32 -0700 (PDT) X-Received: by 2002:a05:6820:60e:b0:67c:3142:b191 with SMTP id 006d021491bc7-67df5d8b201mr184574eaf.24.1774283491520; Mon, 23 Mar 2026 09:31:31 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20260323125824.211615-1-loic.poulain@oss.qualcomm.com> <20260323125824.211615-4-loic.poulain@oss.qualcomm.com> <76edd04d-7bd1-4b42-bea1-79f4b149c0bb@oss.qualcomm.com> In-Reply-To: <76edd04d-7bd1-4b42-bea1-79f4b149c0bb@oss.qualcomm.com> From: Loic Poulain Date: Mon, 23 Mar 2026 17:31:19 +0100 X-Gm-Features: AaiRm53pz500vb6i3cErdYdz3rrYyZsWdQEpVL4m9bzIQb6suv6a2Ww6ErO-Z-A Message-ID: Subject: Re: [RFC PATCH 3/3] arm64: dts: qcom: qcm2290: Add CAMSS OPE node To: Konrad Dybcio Cc: bod@kernel.org, vladimir.zapolskiy@linaro.org, laurent.pinchart@ideasonboard.com, kieran.bingham@ideasonboard.com, robh@kernel.org, krzk+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, johannes.goede@oss.qualcomm.com, mchehab@kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=fKc0HJae c=1 sm=1 tr=0 ts=69c16ae4 cx=c_pps a=lVi5GcDxkcJcfCmEjVJoaw==:117 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=XYktinp8IYMsYWtSA-8A:9 a=jswe0t86hwuQ8JBO:21 a=QEXdDO2ut3YA:10 a=rBiNkAWo9uy_4UTK5NWh:22 X-Proofpoint-GUID: C_82TOf9XaYgt5SkpN-yRV_nMwrA-d74 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDEyNCBTYWx0ZWRfX5nXjskmtC9KN jx63SyoRo4sbjhpIBdP8wzvJJxXkTnXgvMJrcRDHseddyaU3Vdra1bAJR/br4AXL+CEJSvtRqnK Ix+7NmhlYkT16SHdvNXomKV36tCpeDzhgw0fb3BV5TyE+ciduTsWs9hKvR71W4TiCrNnoD1PTJR zK45J8AIP6rah9bQ+WimTPslBEjvOelCAviBB1ALJ1AyZEibKJZSHpaZEClWi614Kv51Ob5nJFt yrn5FyXK7AxcQa3Phrx0G4uhxtagrKnMOF2aLWdRAy08zdsPDvFeneckxslGoAijozJ8HQyd/FZ jwGY966heueeewLN+q9uootBAC9PCeKZMXXkrkOuWZLpqlKRXH+L6Wvoyc6VqVWMo4HdEL4/IvU 4fdDwnGScVs81Up0SBebgAzEg0vn3Xjv2QvAzHwFGc7H90793Xkpf7YI46MW0j6mjIbqDz3ZHsZ BdJzhDSUJid/TGygWcw== X-Proofpoint-ORIG-GUID: C_82TOf9XaYgt5SkpN-yRV_nMwrA-d74 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-23_04,2026-03-23_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 spamscore=0 suspectscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230124 Hi Konrad, On Mon, Mar 23, 2026 at 2:24=E2=80=AFPM Konrad Dybcio wrote: > > On 3/23/26 1:58 PM, Loic Poulain wrote: > > Add the Qualcomm CAMSS Offline Processing Engine (OPE) node for > > QCM2290. The OPE is a memory-to-memory image processing block used in > > offline imaging pipelines. > > > > The node includes register regions, clocks, interconnects, IOMMU > > mappings, power domains, interrupts, and an associated OPP table. > > > > At the moment we assign a fixed rate to GCC_CAMSS_AXI_CLK since this > > clock is shared across multiple CAMSS components and there is currently > > no support for dynamically scaling it. > > > > Signed-off-by: Loic Poulain > > --- > > arch/arm64/boot/dts/qcom/agatti.dtsi | 72 ++++++++++++++++++++++++++++ > > 1 file changed, 72 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts= /qcom/agatti.dtsi > > index f9b46cf1c646..358ebfc99552 100644 > > --- a/arch/arm64/boot/dts/qcom/agatti.dtsi > > +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi > > @@ -1935,6 +1935,78 @@ port@1 { > > }; > > }; > > > > + isp_ope: isp@5c42400 { > > "camss_ope"? Label's don't need to be generic, but they need to be > meaningful - currently one could assume that there's a non-ISP OPE > as well (and I'm intentionally stretching it a bit to prove a point) fair enough. > > > > > + compatible =3D "qcom,qcm2290-camss-ope"; > > + > > + reg =3D <0x0 0x5c42400 0x0 0x200>, > > + <0x0 0x5c46c00 0x0 0x190>, > > + <0x0 0x5c46d90 0x0 0xa00>, > > + <0x0 0x5c42800 0x0 0x4400>, > > + <0x0 0x5c42600 0x0 0x200>; > > + reg-names =3D "top", > > + "bus_read", > > + "bus_write", > > + "pipeline", > > + "qos"; > > This is a completely arbitrary choice, but I think it's easier to compare > against the docs if the reg entries are sorted by the 'reg' (which isn't > always easy to do since that can very between SoCs but this module is not > very common) > > > > + > > + clocks =3D <&gcc GCC_CAMSS_AXI_CLK>, > > + <&gcc GCC_CAMSS_OPE_CLK>, > > + <&gcc GCC_CAMSS_OPE_AHB_CLK>, > > + <&gcc GCC_CAMSS_NRT_AXI_CLK>, > > + <&gcc GCC_CAMSS_TOP_AHB_CLK>; > > + clock-names =3D "axi", "core", "iface", "nrt", "t= op"; > > Similarly, in the arbitrary choice of indices, I think putting "core" > first is "neat" Ok, I thought alphabetical ordering was preferred? > > > + assigned-clocks =3D <&gcc GCC_CAMSS_AXI_CLK>; > > + assigned-clock-rates =3D <300000000>; > > I really think we shouldn't be doing this here for a clock that covers > so much hw Yes, so we probably need some camss framework to scale this, or move this assigned value to camss main node for now. > > [...] > > > > + > > + interrupts =3D = ; > > + > > + interconnects =3D <&bimc MASTER_APPSS_PROC RPM_AC= TIVE_TAG > > + &config_noc SLAVE_CAMERA_CFG RPM= _ACTIVE_TAG>, > > + <&mmnrt_virt MASTER_CAMNOC_SF RPM= _ALWAYS_TAG > > + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>= ; > > + interconnect-names =3D "config", > > + "data"; > > + > > + iommus =3D <&apps_smmu 0x820 0x0>, > > + <&apps_smmu 0x840 0x0>; > > + > > + operating-points-v2 =3D <&ope_opp_table>; > > + power-domains =3D <&gcc GCC_CAMSS_TOP_GDSC>, > > Moving this under camss should let you remove the TOP_GDSC and TOP_AHB (a= nd > perhaps some other) references Yes, will move it and remove what we don't need anymore. > > > + <&rpmpd QCM2290_VDDCX>; > > + power-domain-names =3D "camss", > > + "cx";> + > > + ope_opp_table: opp-table { > > + compatible =3D "operating-points-v2"; > > + > > + opp-19200000 { > > + opp-hz =3D /bits/ 64 <19200000>; > > + required-opps =3D <&rpmpd_opp_min= _svs>; > > + }; > > + > > + opp-200000000 { > > + opp-hz =3D /bits/ 64 <200000000>; > > + required-opps =3D <&rpmpd_opp_svs= >; > > + }; > > + > > + opp-266600000 { > > + opp-hz =3D /bits/ 64 <266600000>; > > + required-opps =3D <&rpmpd_opp_svs= _plus>; > > + }; > > + > > + opp-465000000 { > > + opp-hz =3D /bits/ 64 <465000000>; > > + required-opps =3D <&rpmpd_opp_nom= >; > > + }; > > + > > + opp-580000000 { > > + opp-hz =3D /bits/ 64 <580000000>; > > + required-opps =3D <&rpmpd_opp_tur= bo>; > > + turbo-mode; > > Are we going to act on this property? Otherwise I think it's just a namin= g > collision with Qualcomm's TURBO (which may? have previously??? had some > special implications) 588 MHz is categorized as the "Max Turbo" frequency for the OPE core clock. At some point we may want to enable this only under specific conditions. For now, the OPE driver does not make use of this property. Regards, Loic