From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-177.mta1.migadu.com (out-177.mta1.migadu.com [95.215.58.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA926284665 for ; Fri, 26 Dec 2025 12:00:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.177 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766750432; cv=none; b=GvmIjXDywqfC0QPO9RSCXU6aQ1o2lf+tfhcqn7gKK13JpvJHCQOqZgnM2JIYKG8VUQtBHsGmGKY1HcPb3IA9WeNiFEkI3d6aTttkh1mbPUNMmXoW5k9SxN0OKbS84SYus1AVB2bTNfszipJB1O4Gq3qOmwvlCjUx4vlHyrFctFs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766750432; c=relaxed/simple; bh=uKhfZTz0GoijNXoGGRDwEtdmn8Ncce77Fnm4n0OI0Ko=; h=Mime-Version:Content-Type:Date:Message-Id:Cc:Subject:From:To: References:In-Reply-To; b=XVB/lYTT4q4m4pwNG1Ep8xE67DqmdLl8aaVYd7syyw/jdH/sRtQJ+e/lQJdWP4qxpstistYVOlqI7pIzav/FVy9J1/R+pi9H4eEXIbzchY/0mvDJfxGF/43pQw8kGQRyhBZw3XlOAMQi/CsTAyiSOEsZ8R5W875AWabI+VSHfro= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=cknow-tech.com; spf=pass smtp.mailfrom=cknow-tech.com; dkim=pass (2048-bit key) header.d=cknow-tech.com header.i=@cknow-tech.com header.b=C/A58Ho4; arc=none smtp.client-ip=95.215.58.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=cknow-tech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cknow-tech.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cknow-tech.com header.i=@cknow-tech.com header.b="C/A58Ho4" Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cknow-tech.com; s=key1; t=1766750416; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wCiL6anloSONHQhizAmFuKQ0YGBjJQpCdmeKlo3h5+c=; b=C/A58Ho4/0sxbYSWfMUTH0Dn3ZTEdNlS+amKjOJwQgtW0WijR6aMTbEgs8+ow+efHXNXJk e8IyUzq1rkJODc4YW5pWPXoSoqUoq2wREEtgN4Sm3nBPI+ihNxkokdRrxbnPmcXceC4Q2R pHI0PFJSUTHacoVOZSTGeBd2f6U5Bbe6FXpHZ0yjzIK5e7VeobjBLvNZaBVGE5wqqxCM6P +PwIKWoBDW+bqRjlnUC3mBoM4CtknZfAn73uLmEgHIzQFdrU4e30gtY1amRAranKbsORcP xB2ybKxexps+otWuQJ0H8DNhCa3iA3cRXNEykNuNi/AfZD0eiQkTsStu/dpnlA== Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 26 Dec 2025 13:00:04 +0100 Message-Id: Cc: =?utf-8?q?Olivier_Cr=C3=AAte?= , "Ezequiel Garcia" , "Mauro Carvalho Chehab" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Heiko Stuebner" , "Diederik de Haas" , "Dmitry Osipenko" , "Thomas Gleixner" , "Dragan Simic" , "Chukun Pan" , , , , , Subject: Re: [PATCH v2 2/3] media: rkvdec: Add support for the VDPU346 variant X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: "Diederik de Haas" To: "Christian Hewitt" , "Detlev Casanova" , "Nicolas Dufresne" References: <20251226113140.573759-1-christianshewitt@gmail.com> <20251226113140.573759-3-christianshewitt@gmail.com> In-Reply-To: <20251226113140.573759-3-christianshewitt@gmail.com> X-Migadu-Flow: FLOW_OUT Hi Christian, On Fri Dec 26, 2025 at 12:31 PM CET, Christian Hewitt wrote: > VDPU346 is similar to VDPU381 but with a single core and limited > to 4K60 media. It is also limited to H264 L5.1 and omits AV1 and > AVS2 capabilities. VDPU346 is used with RK3566 and RK3568. > > Signed-off-by: Christian Hewitt > Reviewed-by: Nicolas Dufresne > --- > .../media/platform/rockchip/rkvdec/rkvdec.c | 103 ++++++++++++++++++ > 1 file changed, 103 insertions(+) > > diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/me= dia/platform/rockchip/rkvdec/rkvdec.c > index e547057dc75f..6b39e99d8a8b 100644 > --- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c > +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c > @@ -236,6 +236,62 @@ static const struct rkvdec_ctrls rkvdec_hevc_ctrls = =3D { > .num_ctrls =3D ARRAY_SIZE(rkvdec_hevc_ctrl_descs), > }; > =20 > +static const struct rkvdec_ctrl_desc vdpu346_hevc_ctrl_descs[] =3D { > + { > + .cfg.id =3D V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, > + }, > + { > + .cfg.id =3D V4L2_CID_STATELESS_HEVC_SPS, > + .cfg.ops =3D &rkvdec_ctrl_ops, > + }, > + { > + .cfg.id =3D V4L2_CID_STATELESS_HEVC_PPS, > + }, > + { > + .cfg.id =3D V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, > + }, > + { > + .cfg.id =3D V4L2_CID_STATELESS_HEVC_DECODE_MODE, > + .cfg.min =3D V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, > + .cfg.max =3D V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, > + .cfg.def =3D V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, > + }, > + { > + .cfg.id =3D V4L2_CID_STATELESS_HEVC_START_CODE, > + .cfg.min =3D V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, > + .cfg.def =3D V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, > + .cfg.max =3D V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, > + }, > + { > + .cfg.id =3D V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, > + .cfg.min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, > + .cfg.max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, > + .cfg.menu_skip_mask =3D > + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), > + .cfg.def =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, > + }, > + { > + .cfg.id =3D V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, > + .cfg.min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, > + .cfg.max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, > + }, > + { > + .cfg.id =3D V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS, > + .cfg.ops =3D &rkvdec_ctrl_ops, > + .cfg.dims =3D { 65 }, > + }, > + { > + .cfg.id =3D V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS, > + .cfg.ops =3D &rkvdec_ctrl_ops, > + .cfg.dims =3D { 65 }, > + }, > +}; > + > +static const struct rkvdec_ctrls vdpu346_hevc_ctrls =3D { > + .ctrls =3D vdpu346_hevc_ctrl_descs, > + .num_ctrls =3D ARRAY_SIZE(vdpu346_hevc_ctrl_descs), > +}; > + > static const struct rkvdec_ctrl_desc vdpu38x_hevc_ctrl_descs[] =3D { > { > .cfg.id =3D V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, > @@ -463,6 +519,41 @@ static const struct rkvdec_coded_fmt_desc rk3288_cod= ed_fmts[] =3D { > } > }; > =20 > +static const struct rkvdec_coded_fmt_desc vdpu346_coded_fmts[] =3D { > + { > + .fourcc =3D V4L2_PIX_FMT_HEVC_SLICE, > + .frmsize =3D { > + .min_width =3D 64, > + .max_width =3D 65472, This should be 4096 according to page 469 of RK3568 TRM Part 2 ... > + .step_width =3D 64, > + .min_height =3D 64, > + .max_height =3D 65472, ... and this 2304. > + .step_height =3D 16, > + }, > + .ctrls =3D &vdpu346_hevc_ctrls, > + .ops =3D &rkvdec_vdpu381_hevc_fmt_ops, > + .num_decoded_fmts =3D ARRAY_SIZE(rkvdec_hevc_decoded_fmts), > + .decoded_fmts =3D rkvdec_hevc_decoded_fmts, > + .subsystem_flags =3D VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, > + }, > + { > + .fourcc =3D V4L2_PIX_FMT_H264_SLICE, > + .frmsize =3D { > + .min_width =3D 64, > + .max_width =3D 65520, This too should be 4096 according to page 469 of RK3568 TRM Part 2 ... > + .step_width =3D 64, > + .min_height =3D 64, > + .max_height =3D 65520, ... and this 2304. I guess this also explains the 'green images' Nicolas noticed. > + .step_height =3D 16, > + }, > + .ctrls =3D &rkvdec_h264_ctrls, > + .ops =3D &rkvdec_vdpu381_h264_fmt_ops, > + .num_decoded_fmts =3D ARRAY_SIZE(rkvdec_h264_decoded_fmts), > + .decoded_fmts =3D rkvdec_h264_decoded_fmts, > + .subsystem_flags =3D VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, > + }, I see you've reversed the order of the blocks so that HEVC now comes before the H264 block. While that makes it consistent with what Detlev has in their v7 and with the existing code in the driver ... I actually prefer having H264 before HEVC as the alphabetical sorting order is H264 before HEVC. In the existing code the VP9 'stuff' is listed below H264 and HEVC. But then Detlev should do that too in their patch set ... and 'ideally' the order of the existing code be updated to be alphabetically too. OTOH, a consistent order works for me too. Cheers, Diederik > +}; > + > static const struct rkvdec_coded_fmt_desc vdpu381_coded_fmts[] =3D { > { > .fourcc =3D V4L2_PIX_FMT_HEVC_SLICE, > @@ -1643,6 +1734,14 @@ static const struct rkvdec_variant_ops vdpu381_var= iant_ops =3D { > .flatten_matrices =3D transpose_and_flatten_matrices, > }; > =20 > +static const struct rkvdec_variant vdpu346_variant =3D { > + .coded_fmts =3D vdpu346_coded_fmts, > + .num_coded_fmts =3D ARRAY_SIZE(vdpu346_coded_fmts), > + .rcb_sizes =3D vdpu381_rcb_sizes, > + .num_rcb_sizes =3D ARRAY_SIZE(vdpu381_rcb_sizes), > + .ops =3D &vdpu381_variant_ops, > +}; > + > static const struct rkvdec_variant vdpu381_variant =3D { > .coded_fmts =3D vdpu381_coded_fmts, > .num_coded_fmts =3D ARRAY_SIZE(vdpu381_coded_fmts), > @@ -1691,6 +1790,10 @@ static const struct of_device_id of_rkvdec_match[]= =3D { > .compatible =3D "rockchip,rk3399-vdec", > .data =3D &rk3399_rkvdec_variant, > }, > + { > + .compatible =3D "rockchip,rk3568-vdec", > + .data =3D &vdpu346_variant, > + }, > { > .compatible =3D "rockchip,rk3588-vdec", > .data =3D &vdpu381_variant,