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From: Christoph Hellwig <hch@infradead.org>
To: Dongdong Liu <liudongdong3@huawei.com>
Cc: helgaas@kernel.org, hch@infradead.org, kw@linux.com,
	linux-pci@vger.kernel.org, rajur@chelsio.com,
	hverkuil-cisco@xs4all.nl, linux-media@vger.kernel.org,
	netdev@vger.kernel.org
Subject: Re: [RESEND PATCH V3 1/6] PCI: Use cached Device Capabilities Register
Date: Mon, 14 Jun 2021 06:42:33 +0100	[thread overview]
Message-ID: <YMbsSfQR65TLkbiX@infradead.org> (raw)
In-Reply-To: <1623576555-40338-2-git-send-email-liudongdong3@huawei.com>

On Sun, Jun 13, 2021 at 05:29:10PM +0800, Dongdong Liu wrote:
> It will make sense to store the pcie_devcap value in the pci_dev
> structure instead of reading Device Capabilities Register multiple
> times. The fisrt place to use pcie_devcap is in set_pcie_port_type(),
> get the pcie_devcap value here, then use cached pcie_devcap in the
> needed place.
> 
> Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
> Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
> ---
>  drivers/media/pci/cobalt/cobalt-driver.c |  4 ++--
>  drivers/pci/pci.c                        |  5 +----
>  drivers/pci/pcie/aspm.c                  | 11 ++++-------
>  drivers/pci/probe.c                      | 11 +++--------
>  drivers/pci/quirks.c                     |  3 +--
>  include/linux/pci.h                      |  1 +
>  6 files changed, 12 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/media/pci/cobalt/cobalt-driver.c b/drivers/media/pci/cobalt/cobalt-driver.c
> index 839503e..04e735f 100644
> --- a/drivers/media/pci/cobalt/cobalt-driver.c
> +++ b/drivers/media/pci/cobalt/cobalt-driver.c
> @@ -193,11 +193,11 @@ void cobalt_pcie_status_show(struct cobalt *cobalt)
>  		return;
>  
>  	/* Device */
> -	pcie_capability_read_dword(pci_dev, PCI_EXP_DEVCAP, &capa);
>  	pcie_capability_read_word(pci_dev, PCI_EXP_DEVCTL, &ctrl);
>  	pcie_capability_read_word(pci_dev, PCI_EXP_DEVSTA, &stat);
>  	cobalt_info("PCIe device capability 0x%08x: Max payload %d\n",
> -		    capa, get_payload_size(capa & PCI_EXP_DEVCAP_PAYLOAD));
> +		    capa,
> +		    get_payload_size(pci_dev->pcie_devcap & PCI_EXP_DEVCAP_PAYLOAD));

Overly long line.

> +		if (!(child->pcie_devcap & PCI_EXP_DEVCAP_RBER) && !aspm_force) {

Another one.

Otherwise looks good:

Reviewed-by: Christoph Hellwig <hch@lst.de>

  reply	other threads:[~2021-06-14  5:43 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-13  9:29 [RESEND PATCH V3 0/6] PCI: Enable 10-Bit tag support for PCIe devices Dongdong Liu
2021-06-13  9:29 ` [RESEND PATCH V3 1/6] PCI: Use cached Device Capabilities Register Dongdong Liu
2021-06-14  5:42   ` Christoph Hellwig [this message]
2021-06-15  3:03     ` Dongdong Liu
2021-06-18 14:51   ` kernel test robot
2021-06-21  7:18     ` Dongdong Liu
2021-06-13  9:29 ` [RESEND PATCH V3 2/6] PCI: Use cached Device Capabilities 2 Register Dongdong Liu
2021-06-14  5:49   ` Christoph Hellwig
2021-06-15  3:04     ` Dongdong Liu
2021-06-13  9:29 ` [RESEND PATCH V3 3/6] PCI: Add 10-Bit Tag register definitions Dongdong Liu
2021-06-14  5:50   ` Christoph Hellwig
2021-06-13  9:29 ` [RESEND PATCH V3 4/6] PCI: Enable 10-Bit tag support for PCIe Endpoint devices Dongdong Liu
2021-06-14  5:54   ` Christoph Hellwig
2021-06-15  3:07     ` Dongdong Liu
2021-06-13  9:29 ` [RESEND PATCH V3 5/6] PCI/IOV: Enable 10-Bit tag support for PCIe VF devices Dongdong Liu
2021-06-14  5:55   ` Christoph Hellwig
2021-06-13  9:29 ` [RESEND PATCH V3 6/6] PCI: Enable 10-Bit tag support for PCIe RP devices Dongdong Liu
2021-06-14  5:57   ` Christoph Hellwig
2021-06-15  3:08     ` Dongdong Liu

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