From: Ricardo Ribalda <ribalda@chromium.org>
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-media@vger.kernel.org,
Dafna Hirschfeld <dafna@fastmail.com>,
Heiko Stuebner <heiko@sntech.de>,
Paul Elder <paul.elder@ideasonboard.com>,
Tomasz Figa <tfiga@google.com>,
linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v4 11/21] media: rkisp1: resizer: Simplify register access
Date: Mon, 25 Apr 2022 11:58:58 +0200 [thread overview]
Message-ID: <YmZw4gj7W5x/WOLE@gmail.com> (raw)
In-Reply-To: <20220421234240.1694-12-laurent.pinchart@ideasonboard.com>
Laurent Pinchart wrote:
> The registers for the mainpath and selfpath resizers are located at the
> same offset from the instance-specific base. Use this to simplify
> register access, removing the need to store per-register offsets in the
> rkisp1_rsz_config structure.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ricardo Ribalda <ribalda@chromium.org>
> ---
> Changes since v1:
>
> - Fix order of arguments to write function
> ---
> .../platform/rockchip/rkisp1/rkisp1-common.h | 2 +
> .../platform/rockchip/rkisp1/rkisp1-regs.h | 67 +++-----
> .../platform/rockchip/rkisp1/rkisp1-resizer.c | 161 ++++++------------
> 3 files changed, 75 insertions(+), 155 deletions(-)
>
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> index 941580c9c4e0..3b36ab05ac34 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> @@ -313,6 +313,7 @@ struct rkisp1_params {
> * struct rkisp1_resizer - Resizer subdev
> *
> * @sd: v4l2_subdev variable
> + * @regs_base: base register address offset
> * @id: id of the resizer, one of RKISP1_SELFPATH, RKISP1_MAINPATH
> * @rkisp1: pointer to the rkisp1 device
> * @pads: media pads
> @@ -323,6 +324,7 @@ struct rkisp1_params {
> */
> struct rkisp1_resizer {
> struct v4l2_subdev sd;
> + u32 regs_base;
> enum rkisp1_stream_id id;
> struct rkisp1_device *rkisp1;
> struct media_pad pads[RKISP1_RSZ_PAD_MAX];
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> index 0f6ea67b4d5a..a93d0127b813 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> @@ -905,52 +905,29 @@
> #define RKISP1_CIF_DUAL_CROP_S_V_SIZE_SHD (RKISP1_CIF_DUAL_CROP_BASE + 0x00000040)
>
> #define RKISP1_CIF_MRSZ_BASE 0x00000C00
> -#define RKISP1_CIF_MRSZ_CTRL (RKISP1_CIF_MRSZ_BASE + 0x00000000)
> -#define RKISP1_CIF_MRSZ_SCALE_HY (RKISP1_CIF_MRSZ_BASE + 0x00000004)
> -#define RKISP1_CIF_MRSZ_SCALE_HCB (RKISP1_CIF_MRSZ_BASE + 0x00000008)
> -#define RKISP1_CIF_MRSZ_SCALE_HCR (RKISP1_CIF_MRSZ_BASE + 0x0000000C)
> -#define RKISP1_CIF_MRSZ_SCALE_VY (RKISP1_CIF_MRSZ_BASE + 0x00000010)
> -#define RKISP1_CIF_MRSZ_SCALE_VC (RKISP1_CIF_MRSZ_BASE + 0x00000014)
> -#define RKISP1_CIF_MRSZ_PHASE_HY (RKISP1_CIF_MRSZ_BASE + 0x00000018)
> -#define RKISP1_CIF_MRSZ_PHASE_HC (RKISP1_CIF_MRSZ_BASE + 0x0000001C)
> -#define RKISP1_CIF_MRSZ_PHASE_VY (RKISP1_CIF_MRSZ_BASE + 0x00000020)
> -#define RKISP1_CIF_MRSZ_PHASE_VC (RKISP1_CIF_MRSZ_BASE + 0x00000024)
> -#define RKISP1_CIF_MRSZ_SCALE_LUT_ADDR (RKISP1_CIF_MRSZ_BASE + 0x00000028)
> -#define RKISP1_CIF_MRSZ_SCALE_LUT (RKISP1_CIF_MRSZ_BASE + 0x0000002C)
> -#define RKISP1_CIF_MRSZ_CTRL_SHD (RKISP1_CIF_MRSZ_BASE + 0x00000030)
> -#define RKISP1_CIF_MRSZ_SCALE_HY_SHD (RKISP1_CIF_MRSZ_BASE + 0x00000034)
> -#define RKISP1_CIF_MRSZ_SCALE_HCB_SHD (RKISP1_CIF_MRSZ_BASE + 0x00000038)
> -#define RKISP1_CIF_MRSZ_SCALE_HCR_SHD (RKISP1_CIF_MRSZ_BASE + 0x0000003C)
> -#define RKISP1_CIF_MRSZ_SCALE_VY_SHD (RKISP1_CIF_MRSZ_BASE + 0x00000040)
> -#define RKISP1_CIF_MRSZ_SCALE_VC_SHD (RKISP1_CIF_MRSZ_BASE + 0x00000044)
> -#define RKISP1_CIF_MRSZ_PHASE_HY_SHD (RKISP1_CIF_MRSZ_BASE + 0x00000048)
> -#define RKISP1_CIF_MRSZ_PHASE_HC_SHD (RKISP1_CIF_MRSZ_BASE + 0x0000004C)
> -#define RKISP1_CIF_MRSZ_PHASE_VY_SHD (RKISP1_CIF_MRSZ_BASE + 0x00000050)
> -#define RKISP1_CIF_MRSZ_PHASE_VC_SHD (RKISP1_CIF_MRSZ_BASE + 0x00000054)
> -
> #define RKISP1_CIF_SRSZ_BASE 0x00001000
> -#define RKISP1_CIF_SRSZ_CTRL (RKISP1_CIF_SRSZ_BASE + 0x00000000)
> -#define RKISP1_CIF_SRSZ_SCALE_HY (RKISP1_CIF_SRSZ_BASE + 0x00000004)
> -#define RKISP1_CIF_SRSZ_SCALE_HCB (RKISP1_CIF_SRSZ_BASE + 0x00000008)
> -#define RKISP1_CIF_SRSZ_SCALE_HCR (RKISP1_CIF_SRSZ_BASE + 0x0000000C)
> -#define RKISP1_CIF_SRSZ_SCALE_VY (RKISP1_CIF_SRSZ_BASE + 0x00000010)
> -#define RKISP1_CIF_SRSZ_SCALE_VC (RKISP1_CIF_SRSZ_BASE + 0x00000014)
> -#define RKISP1_CIF_SRSZ_PHASE_HY (RKISP1_CIF_SRSZ_BASE + 0x00000018)
> -#define RKISP1_CIF_SRSZ_PHASE_HC (RKISP1_CIF_SRSZ_BASE + 0x0000001C)
> -#define RKISP1_CIF_SRSZ_PHASE_VY (RKISP1_CIF_SRSZ_BASE + 0x00000020)
> -#define RKISP1_CIF_SRSZ_PHASE_VC (RKISP1_CIF_SRSZ_BASE + 0x00000024)
> -#define RKISP1_CIF_SRSZ_SCALE_LUT_ADDR (RKISP1_CIF_SRSZ_BASE + 0x00000028)
> -#define RKISP1_CIF_SRSZ_SCALE_LUT (RKISP1_CIF_SRSZ_BASE + 0x0000002C)
> -#define RKISP1_CIF_SRSZ_CTRL_SHD (RKISP1_CIF_SRSZ_BASE + 0x00000030)
> -#define RKISP1_CIF_SRSZ_SCALE_HY_SHD (RKISP1_CIF_SRSZ_BASE + 0x00000034)
> -#define RKISP1_CIF_SRSZ_SCALE_HCB_SHD (RKISP1_CIF_SRSZ_BASE + 0x00000038)
> -#define RKISP1_CIF_SRSZ_SCALE_HCR_SHD (RKISP1_CIF_SRSZ_BASE + 0x0000003C)
> -#define RKISP1_CIF_SRSZ_SCALE_VY_SHD (RKISP1_CIF_SRSZ_BASE + 0x00000040)
> -#define RKISP1_CIF_SRSZ_SCALE_VC_SHD (RKISP1_CIF_SRSZ_BASE + 0x00000044)
> -#define RKISP1_CIF_SRSZ_PHASE_HY_SHD (RKISP1_CIF_SRSZ_BASE + 0x00000048)
> -#define RKISP1_CIF_SRSZ_PHASE_HC_SHD (RKISP1_CIF_SRSZ_BASE + 0x0000004C)
> -#define RKISP1_CIF_SRSZ_PHASE_VY_SHD (RKISP1_CIF_SRSZ_BASE + 0x00000050)
> -#define RKISP1_CIF_SRSZ_PHASE_VC_SHD (RKISP1_CIF_SRSZ_BASE + 0x00000054)
> +#define RKISP1_CIF_RSZ_CTRL 0x0000
> +#define RKISP1_CIF_RSZ_SCALE_HY 0x0004
> +#define RKISP1_CIF_RSZ_SCALE_HCB 0x0008
> +#define RKISP1_CIF_RSZ_SCALE_HCR 0x000C
> +#define RKISP1_CIF_RSZ_SCALE_VY 0x0010
> +#define RKISP1_CIF_RSZ_SCALE_VC 0x0014
> +#define RKISP1_CIF_RSZ_PHASE_HY 0x0018
> +#define RKISP1_CIF_RSZ_PHASE_HC 0x001C
> +#define RKISP1_CIF_RSZ_PHASE_VY 0x0020
> +#define RKISP1_CIF_RSZ_PHASE_VC 0x0024
> +#define RKISP1_CIF_RSZ_SCALE_LUT_ADDR 0x0028
> +#define RKISP1_CIF_RSZ_SCALE_LUT 0x002C
> +#define RKISP1_CIF_RSZ_CTRL_SHD 0x0030
> +#define RKISP1_CIF_RSZ_SCALE_HY_SHD 0x0034
> +#define RKISP1_CIF_RSZ_SCALE_HCB_SHD 0x0038
> +#define RKISP1_CIF_RSZ_SCALE_HCR_SHD 0x003C
> +#define RKISP1_CIF_RSZ_SCALE_VY_SHD 0x0040
> +#define RKISP1_CIF_RSZ_SCALE_VC_SHD 0x0044
> +#define RKISP1_CIF_RSZ_PHASE_HY_SHD 0x0048
> +#define RKISP1_CIF_RSZ_PHASE_HC_SHD 0x004C
> +#define RKISP1_CIF_RSZ_PHASE_VY_SHD 0x0050
> +#define RKISP1_CIF_RSZ_PHASE_VC_SHD 0x0054
>
> #define RKISP1_CIF_MI_BASE 0x00001400
> #define RKISP1_CIF_MI_CTRL (RKISP1_CIF_MI_BASE + 0x00000000)
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
> index b88d579a283c..ac1b357a2a3a 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
> @@ -59,30 +59,6 @@ struct rkisp1_rsz_config {
> const int min_rsz_width;
> const int min_rsz_height;
> /* registers */
> - struct {
> - u32 ctrl;
> - u32 ctrl_shd;
> - u32 scale_hy;
> - u32 scale_hcr;
> - u32 scale_hcb;
> - u32 scale_vy;
> - u32 scale_vc;
> - u32 scale_lut;
> - u32 scale_lut_addr;
> - u32 scale_hy_shd;
> - u32 scale_hcr_shd;
> - u32 scale_hcb_shd;
> - u32 scale_vy_shd;
> - u32 scale_vc_shd;
> - u32 phase_hy;
> - u32 phase_hc;
> - u32 phase_vy;
> - u32 phase_vc;
> - u32 phase_hy_shd;
> - u32 phase_hc_shd;
> - u32 phase_vy_shd;
> - u32 phase_vc_shd;
> - } rsz;
> struct {
> u32 ctrl;
> u32 yuvmode_mask;
> @@ -101,30 +77,6 @@ static const struct rkisp1_rsz_config rkisp1_rsz_config_mp = {
> .min_rsz_width = RKISP1_RSZ_SRC_MIN_WIDTH,
> .min_rsz_height = RKISP1_RSZ_SRC_MIN_HEIGHT,
> /* registers */
> - .rsz = {
> - .ctrl = RKISP1_CIF_MRSZ_CTRL,
> - .scale_hy = RKISP1_CIF_MRSZ_SCALE_HY,
> - .scale_hcr = RKISP1_CIF_MRSZ_SCALE_HCR,
> - .scale_hcb = RKISP1_CIF_MRSZ_SCALE_HCB,
> - .scale_vy = RKISP1_CIF_MRSZ_SCALE_VY,
> - .scale_vc = RKISP1_CIF_MRSZ_SCALE_VC,
> - .scale_lut = RKISP1_CIF_MRSZ_SCALE_LUT,
> - .scale_lut_addr = RKISP1_CIF_MRSZ_SCALE_LUT_ADDR,
> - .scale_hy_shd = RKISP1_CIF_MRSZ_SCALE_HY_SHD,
> - .scale_hcr_shd = RKISP1_CIF_MRSZ_SCALE_HCR_SHD,
> - .scale_hcb_shd = RKISP1_CIF_MRSZ_SCALE_HCB_SHD,
> - .scale_vy_shd = RKISP1_CIF_MRSZ_SCALE_VY_SHD,
> - .scale_vc_shd = RKISP1_CIF_MRSZ_SCALE_VC_SHD,
> - .phase_hy = RKISP1_CIF_MRSZ_PHASE_HY,
> - .phase_hc = RKISP1_CIF_MRSZ_PHASE_HC,
> - .phase_vy = RKISP1_CIF_MRSZ_PHASE_VY,
> - .phase_vc = RKISP1_CIF_MRSZ_PHASE_VC,
> - .ctrl_shd = RKISP1_CIF_MRSZ_CTRL_SHD,
> - .phase_hy_shd = RKISP1_CIF_MRSZ_PHASE_HY_SHD,
> - .phase_hc_shd = RKISP1_CIF_MRSZ_PHASE_HC_SHD,
> - .phase_vy_shd = RKISP1_CIF_MRSZ_PHASE_VY_SHD,
> - .phase_vc_shd = RKISP1_CIF_MRSZ_PHASE_VC_SHD,
> - },
> .dual_crop = {
> .ctrl = RKISP1_CIF_DUAL_CROP_CTRL,
> .yuvmode_mask = RKISP1_CIF_DUAL_CROP_MP_MODE_YUV,
> @@ -143,30 +95,6 @@ static const struct rkisp1_rsz_config rkisp1_rsz_config_sp = {
> .min_rsz_width = RKISP1_RSZ_SRC_MIN_WIDTH,
> .min_rsz_height = RKISP1_RSZ_SRC_MIN_HEIGHT,
> /* registers */
> - .rsz = {
> - .ctrl = RKISP1_CIF_SRSZ_CTRL,
> - .scale_hy = RKISP1_CIF_SRSZ_SCALE_HY,
> - .scale_hcr = RKISP1_CIF_SRSZ_SCALE_HCR,
> - .scale_hcb = RKISP1_CIF_SRSZ_SCALE_HCB,
> - .scale_vy = RKISP1_CIF_SRSZ_SCALE_VY,
> - .scale_vc = RKISP1_CIF_SRSZ_SCALE_VC,
> - .scale_lut = RKISP1_CIF_SRSZ_SCALE_LUT,
> - .scale_lut_addr = RKISP1_CIF_SRSZ_SCALE_LUT_ADDR,
> - .scale_hy_shd = RKISP1_CIF_SRSZ_SCALE_HY_SHD,
> - .scale_hcr_shd = RKISP1_CIF_SRSZ_SCALE_HCR_SHD,
> - .scale_hcb_shd = RKISP1_CIF_SRSZ_SCALE_HCB_SHD,
> - .scale_vy_shd = RKISP1_CIF_SRSZ_SCALE_VY_SHD,
> - .scale_vc_shd = RKISP1_CIF_SRSZ_SCALE_VC_SHD,
> - .phase_hy = RKISP1_CIF_SRSZ_PHASE_HY,
> - .phase_hc = RKISP1_CIF_SRSZ_PHASE_HC,
> - .phase_vy = RKISP1_CIF_SRSZ_PHASE_VY,
> - .phase_vc = RKISP1_CIF_SRSZ_PHASE_VC,
> - .ctrl_shd = RKISP1_CIF_SRSZ_CTRL_SHD,
> - .phase_hy_shd = RKISP1_CIF_SRSZ_PHASE_HY_SHD,
> - .phase_hc_shd = RKISP1_CIF_SRSZ_PHASE_HC_SHD,
> - .phase_vy_shd = RKISP1_CIF_SRSZ_PHASE_VY_SHD,
> - .phase_vc_shd = RKISP1_CIF_SRSZ_PHASE_VC_SHD,
> - },
> .dual_crop = {
> .ctrl = RKISP1_CIF_DUAL_CROP_CTRL,
> .yuvmode_mask = RKISP1_CIF_DUAL_CROP_SP_MODE_YUV,
> @@ -178,6 +106,17 @@ static const struct rkisp1_rsz_config rkisp1_rsz_config_sp = {
> },
> };
>
> +static inline u32 rkisp1_rsz_read(struct rkisp1_resizer *rsz, u32 offset)
> +{
> + return rkisp1_read(rsz->rkisp1, rsz->regs_base + offset);
> +}
> +
> +static inline void rkisp1_rsz_write(struct rkisp1_resizer *rsz, u32 offset,
> + u32 value)
> +{
> + rkisp1_write(rsz->rkisp1, rsz->regs_base + offset, value);
> +}
> +
> static struct v4l2_mbus_framefmt *
> rkisp1_rsz_get_pad_fmt(struct rkisp1_resizer *rsz,
> struct v4l2_subdev_state *sd_state,
> @@ -277,39 +216,39 @@ static void rkisp1_rsz_dump_regs(struct rkisp1_resizer *rsz)
> "RSZ_PHASE_HC %d/%d\n"
> "RSZ_PHASE_VY %d/%d\n"
> "RSZ_PHASE_VC %d/%d\n",
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.ctrl),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.ctrl_shd),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hy),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hy_shd),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hcb),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hcb_shd),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hcr),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hcr_shd),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_vy),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_vy_shd),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_vc),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_vc_shd),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_hy),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_hy_shd),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_hc),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_hc_shd),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_vy),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_vy_shd),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_vc),
> - rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_vc_shd));
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_CTRL),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_CTRL_SHD),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_SCALE_HY),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_SCALE_HY_SHD),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_SCALE_HCB),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_SCALE_HCB_SHD),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_SCALE_HCR),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_SCALE_HCR_SHD),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_SCALE_VY),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_SCALE_VY_SHD),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_SCALE_VC),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_SCALE_VC_SHD),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_PHASE_HY),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_PHASE_HY_SHD),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_PHASE_HC),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_PHASE_HC_SHD),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_PHASE_VY),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_PHASE_VY_SHD),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_PHASE_VC),
> + rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_PHASE_VC_SHD));
> }
>
> static void rkisp1_rsz_update_shadow(struct rkisp1_resizer *rsz,
> enum rkisp1_shadow_regs_when when)
> {
> - u32 ctrl_cfg = rkisp1_read(rsz->rkisp1, rsz->config->rsz.ctrl);
> + u32 ctrl_cfg = rkisp1_rsz_read(rsz, RKISP1_CIF_RSZ_CTRL);
>
> if (when == RKISP1_SHADOW_REGS_ASYNC)
> ctrl_cfg |= RKISP1_CIF_RSZ_CTRL_CFG_UPD_AUTO;
> else
> ctrl_cfg |= RKISP1_CIF_RSZ_CTRL_CFG_UPD;
>
> - rkisp1_write(rsz->rkisp1, rsz->config->rsz.ctrl, ctrl_cfg);
> + rkisp1_rsz_write(rsz, RKISP1_CIF_RSZ_CTRL, ctrl_cfg);
> }
>
> static u32 rkisp1_rsz_calc_ratio(u32 len_sink, u32 len_src)
> @@ -325,7 +264,7 @@ static u32 rkisp1_rsz_calc_ratio(u32 len_sink, u32 len_src)
> static void rkisp1_rsz_disable(struct rkisp1_resizer *rsz,
> enum rkisp1_shadow_regs_when when)
> {
> - rkisp1_write(rsz->rkisp1, rsz->config->rsz.ctrl, 0);
> + rkisp1_rsz_write(rsz, RKISP1_CIF_RSZ_CTRL, 0);
>
> if (when == RKISP1_SHADOW_REGS_SYNC)
> rkisp1_rsz_update_shadow(rsz, when);
> @@ -338,20 +277,19 @@ static void rkisp1_rsz_config_regs(struct rkisp1_resizer *rsz,
> struct v4l2_rect *src_c,
> enum rkisp1_shadow_regs_when when)
> {
> - struct rkisp1_device *rkisp1 = rsz->rkisp1;
> u32 ratio, rsz_ctrl = 0;
> unsigned int i;
>
> /* No phase offset */
> - rkisp1_write(rkisp1, rsz->config->rsz.phase_hy, 0);
> - rkisp1_write(rkisp1, rsz->config->rsz.phase_hc, 0);
> - rkisp1_write(rkisp1, rsz->config->rsz.phase_vy, 0);
> - rkisp1_write(rkisp1, rsz->config->rsz.phase_vc, 0);
> + rkisp1_rsz_write(rsz, RKISP1_CIF_RSZ_PHASE_HY, 0);
> + rkisp1_rsz_write(rsz, RKISP1_CIF_RSZ_PHASE_HC, 0);
> + rkisp1_rsz_write(rsz, RKISP1_CIF_RSZ_PHASE_VY, 0);
> + rkisp1_rsz_write(rsz, RKISP1_CIF_RSZ_PHASE_VC, 0);
>
> /* Linear interpolation */
> for (i = 0; i < 64; i++) {
> - rkisp1_write(rkisp1, rsz->config->rsz.scale_lut_addr, i);
> - rkisp1_write(rkisp1, rsz->config->rsz.scale_lut, i);
> + rkisp1_rsz_write(rsz, RKISP1_CIF_RSZ_SCALE_LUT_ADDR, i);
> + rkisp1_rsz_write(rsz, RKISP1_CIF_RSZ_SCALE_LUT, i);
> }
>
> if (sink_y->width != src_y->width) {
> @@ -359,7 +297,7 @@ static void rkisp1_rsz_config_regs(struct rkisp1_resizer *rsz,
> if (sink_y->width < src_y->width)
> rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_HY_UP;
> ratio = rkisp1_rsz_calc_ratio(sink_y->width, src_y->width);
> - rkisp1_write(rkisp1, rsz->config->rsz.scale_hy, ratio);
> + rkisp1_rsz_write(rsz, RKISP1_CIF_RSZ_SCALE_HY, ratio);
> }
>
> if (sink_c->width != src_c->width) {
> @@ -367,8 +305,8 @@ static void rkisp1_rsz_config_regs(struct rkisp1_resizer *rsz,
> if (sink_c->width < src_c->width)
> rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_HC_UP;
> ratio = rkisp1_rsz_calc_ratio(sink_c->width, src_c->width);
> - rkisp1_write(rkisp1, rsz->config->rsz.scale_hcb, ratio);
> - rkisp1_write(rkisp1, rsz->config->rsz.scale_hcr, ratio);
> + rkisp1_rsz_write(rsz, RKISP1_CIF_RSZ_SCALE_HCB, ratio);
> + rkisp1_rsz_write(rsz, RKISP1_CIF_RSZ_SCALE_HCR, ratio);
> }
>
> if (sink_y->height != src_y->height) {
> @@ -376,7 +314,7 @@ static void rkisp1_rsz_config_regs(struct rkisp1_resizer *rsz,
> if (sink_y->height < src_y->height)
> rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_VY_UP;
> ratio = rkisp1_rsz_calc_ratio(sink_y->height, src_y->height);
> - rkisp1_write(rkisp1, rsz->config->rsz.scale_vy, ratio);
> + rkisp1_rsz_write(rsz, RKISP1_CIF_RSZ_SCALE_VY, ratio);
> }
>
> if (sink_c->height != src_c->height) {
> @@ -384,10 +322,10 @@ static void rkisp1_rsz_config_regs(struct rkisp1_resizer *rsz,
> if (sink_c->height < src_c->height)
> rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_VC_UP;
> ratio = rkisp1_rsz_calc_ratio(sink_c->height, src_c->height);
> - rkisp1_write(rkisp1, rsz->config->rsz.scale_vc, ratio);
> + rkisp1_rsz_write(rsz, RKISP1_CIF_RSZ_SCALE_VC, ratio);
> }
>
> - rkisp1_write(rkisp1, rsz->config->rsz.ctrl, rsz_ctrl);
> + rkisp1_rsz_write(rsz, RKISP1_CIF_RSZ_CTRL, rsz_ctrl);
>
> rkisp1_rsz_update_shadow(rsz, when);
> }
> @@ -803,10 +741,13 @@ static int rkisp1_rsz_register(struct rkisp1_resizer *rsz)
> struct v4l2_subdev *sd = &rsz->sd;
> int ret;
>
> - if (rsz->id == RKISP1_SELFPATH)
> + if (rsz->id == RKISP1_SELFPATH) {
> + rsz->regs_base = RKISP1_CIF_SRSZ_BASE;
> rsz->config = &rkisp1_rsz_config_sp;
Why not moving the base_address to ->config ?
> - else
> + } else {
> + rsz->regs_base = RKISP1_CIF_MRSZ_BASE;
> rsz->config = &rkisp1_rsz_config_mp;
> + }
>
> v4l2_subdev_init(sd, &rkisp1_rsz_ops);
> sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
> --
> Regards,
>
> Laurent Pinchart
>
>
next prev parent reply other threads:[~2022-04-25 9:59 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-21 23:42 [PATCH v4 00/21] media: rkisp1: Misc bug fixes and cleanups Laurent Pinchart
2022-04-21 23:42 ` [PATCH v4 01/21] media: rkisp1: capture: Initialize entity before video device Laurent Pinchart
2022-04-25 7:52 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 02/21] media: rkisp1: capture: Fix and simplify (un)registration Laurent Pinchart
2022-04-25 9:34 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 03/21] media: rkisp1: isp: " Laurent Pinchart
2022-04-25 9:36 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 04/21] media: rkisp1: resizer: " Laurent Pinchart
2022-04-25 9:37 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 05/21] media: rkisp1: params: " Laurent Pinchart
2022-04-25 9:39 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 06/21] media: rkisp1: stats: Simplify (un)registration Laurent Pinchart
2022-04-25 9:44 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 07/21] media: rkisp1: Simplify rkisp1_entities_register() error path Laurent Pinchart
2022-04-25 9:45 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 08/21] media: rkisp1: regs: Don't use BIT() macro for multi-bit register fields Laurent Pinchart
2022-04-25 9:50 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 09/21] media: rkisp1: regs: Rename CCL, ICCL and IRCL registers with VI_ prefix Laurent Pinchart
2022-04-25 9:51 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 10/21] media: rkisp1: Swap value and address arguments to rkisp1_write() Laurent Pinchart
2022-04-25 9:53 ` Ricardo Ribalda
2022-04-25 18:59 ` Laurent Pinchart
2022-04-21 23:42 ` [PATCH v4 11/21] media: rkisp1: resizer: Simplify register access Laurent Pinchart
2022-04-25 9:58 ` Ricardo Ribalda [this message]
2022-04-21 23:42 ` [PATCH v4 12/21] media: rkisp1: Move debugfs code to a separate file Laurent Pinchart
2022-04-25 10:54 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 13/21] media: rkisp1: Compile debugfs support conditionally Laurent Pinchart
2022-04-25 10:58 ` Ricardo Ribalda
2022-04-25 19:08 ` Laurent Pinchart
2022-04-26 7:33 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 14/21] media: rkisp1: debug: Collect input status by sampling ISP_FLAGS_SHD Laurent Pinchart
2022-04-25 11:08 ` Ricardo Ribalda
2022-04-25 20:13 ` Laurent Pinchart
2022-04-21 23:42 ` [PATCH v4 15/21] media: rkisp1: debug: Add debugfs files to dump core and ISP registers Laurent Pinchart
2022-04-25 11:13 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 16/21] media: rkisp1: debug: Move resizer register dump to debugfs Laurent Pinchart
2022-04-25 11:16 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 17/21] media: rkisp1: debug: Consolidate reg dumps for shadow registers Laurent Pinchart
2022-04-25 11:45 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 18/21] media: rkisp1: debug: Compute max register length name dynamically Laurent Pinchart
2022-04-25 11:49 ` Ricardo Ribalda
2022-04-25 19:05 ` Laurent Pinchart
2022-04-25 21:01 ` [PATCH v4.1 18/21] media: rkisp1: debug: Update max register name length Laurent Pinchart
2022-04-26 7:39 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 19/21] media: rkisp1: capture: Bypass the main device for handling querycap Laurent Pinchart
2022-04-25 11:51 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 20/21] media: rkisp1: Align macro definitions Laurent Pinchart
2022-04-25 11:52 ` Ricardo Ribalda
2022-04-21 23:42 ` [PATCH v4 21/21] media: rkisp1: Drop parentheses and fix indentation in rkisp1_probe() Laurent Pinchart
2022-04-25 8:30 ` Ricardo Ribalda
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