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X-CSE-ConnectionGUID: ybaABSk7RGyTpweZspyaVw== X-CSE-MsgGUID: tBH219ieT4mX1xEidJlOBA== X-IronPort-AV: E=McAfee;i="6700,10204,11369"; a="46366259" X-IronPort-AV: E=Sophos;i="6.14,238,1736841600"; d="scan'208";a="46366259" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Mar 2025 03:13:36 -0700 X-CSE-ConnectionGUID: v2AEapuIRVGpcC2EwYDGJg== X-CSE-MsgGUID: 3Wzl8BTgT76oVqpNZ1tqsA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,238,1736841600"; d="scan'208";a="120312756" Received: from turnipsi.fi.intel.com (HELO kekkonen.fi.intel.com) ([10.237.72.44]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Mar 2025 03:13:33 -0700 Received: from kekkonen.localdomain (localhost [127.0.0.1]) by kekkonen.fi.intel.com (Postfix) with ESMTP id 5FC7711F828; Tue, 11 Mar 2025 12:13:31 +0200 (EET) Date: Tue, 11 Mar 2025 10:13:31 +0000 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo From: Sakari Ailus To: Tarang Raval Cc: "Shravan.Chippa@microchip.com" , "laurent.pinchart@ideasonboard.com" , "kieran.bingham@ideasonboard.com" , "mchehab@kernel.org" , "hverkuil@xs4all.nl" , "umang.jain@ideasonboard.com" , "zhi.mao@mediatek.com" , "julien.massot@collabora.com" , "mike.rudenko@gmail.com" , "benjamin.mugnier@foss.st.com" , "linux-media@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH 2/6] media: i2c: imx334: Convert to CCI register access helpers Message-ID: References: <20250310071751.151382-1-tarang.raval@siliconsignals.io> <20250310071751.151382-3-tarang.raval@siliconsignals.io> <20250311063849.GB29331@pendragon.ideasonboard.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Hi Tarang, On Tue, Mar 11, 2025 at 10:05:12AM +0000, Tarang Raval wrote: > Hi Sakari, > > > On Tue, Mar 11, 2025 at 06:51:48AM +0000, Shravan.Chippa@microchip.com wrote: > > > Hi Laurent, > > > > > > > -----Original Message----- > > > > From: Laurent Pinchart > > > > Sent: Tuesday, March 11, 2025 12:09 PM > > > > To: shravan Chippa - I35088 > > > > Cc: tarang.raval@siliconsignals.io; sakari.ailus@linux.intel.com; > > > > kieran.bingham@ideasonboard.com; mchehab@kernel.org; > > > > hverkuil@xs4all.nl; umang.jain@ideasonboard.com; zhi.mao@mediatek.com; > > > > julien.massot@collabora.com; mike.rudenko@gmail.com; > > > > benjamin.mugnier@foss.st.com; linux-media@vger.kernel.org; linux- > > > > kernel@vger.kernel.org > > > > Subject: Re: [PATCH 2/6] media: i2c: imx334: Convert to CCI register access > > > > helpers > > > > > > > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > > > > content is safe > > > > > > > > Hi Shravan, > > > > > > > > On Tue, Mar 11, 2025 at 06:14:28AM +0000, Shravan.Chippa@microchip.com > > > > wrote: > > > > > Hi Tarang, > > > > > > > > > > Thanks for the patch series with CCI register access helpers on top of > > > > > my patches I have tested (1080p,720p, 480p resolution only) and > > > > > working on my board with small PLL changes to make it compatible with > > > > > pfsoc board (mpfs-video-kit). > > > > > > > > Could you please provide more information about what those PLL changes are > > > > ? > > > > > > Here is the change for mpfs-video-kit board. > > > > > > diff --git a/drivers/media/i2c/imx334.c b/drivers/media/i2c/imx334.c > > > index 375367314416..30470dbd1f3c 100644 > > > --- a/drivers/media/i2c/imx334.c > > > +++ b/drivers/media/i2c/imx334.c > > > @@ -236,9 +236,9 @@ static const struct cci_reg_sequence common_mode_regs[] = { > > >         { IMX334_REG_XVS_XHS_OUTSEL, 0x20}, > > >         { IMX334_REG_XVS_XHS_DRV, 0x0f}, > > >         { IMX334_REG_BCWAIT_TIME, 0x3b}, > > > -       { IMX334_REG_CPWAIT_TIME, 0x2a}, > > > +       { IMX334_REG_CPWAIT_TIME, 0x29}, > > > > A patch converting the driver to use V4L2 CCI / human-readable register > > names should not change the values written. > > This change is not from my patch. > > You can recheck Shravan’s second patch, there is no change in the > CPWAIT_TIME value from my patch or his. > > The change Shravan mentioned was made locally to ensure compatibility > with the mpfs-video-kit board, as Laurent requested. > That’s why he provided those details. Right. I don't know what this or the other change do exactly, but presumably the other one is a clock tree divider that reduces the link frequency (or pixel rate in pixel array). That should be handled separately. -- Sakari Ailus