Re: [PATCH RESEND v8 16/21] media: i2c: maxim-serdes: add MAX96724 driver

[Cory Keitz <ckeitz@amazon.com>]

On Mon, Dec 08, 2025 at 04:13:08PM +0200, Dumitru Ceclan via B4 Relay wrote:
> +static int max96724_init_phy(struct max_des *des, struct max_des_phy *phy)
> +{
> +	struct max96724_priv *priv = des_to_priv(des);
> +	bool is_cphy = phy->bus_type == V4L2_MBUS_CSI2_CPHY;
> +	unsigned int num_data_lanes = phy->mipi.num_data_lanes;
> +	unsigned int dpll_freq = phy->link_frequency * 2;

This unconditionally doubles the link frequency for the DPLL, which is
correct for D-PHY (DDR clocking) but incorrect for C-PHY. Per the
MAX96724 User Guide:

  D-PHY: "Clock freq is half; Data rate is equivalent bps/lane."
         e.g. 00010 = 200MHz DPLL, 200Mbps/lane data rate.

  C-PHY: "2.28bits/symbol."
         e.g. 00010 = 200MHz DPLL, 456Mbps/lane data rate.

For C-PHY the DPLL value equals the symbol rate, which is the link
frequency directly. Should be:

        unsigned int dpll_freq = is_cphy ? phy->link_frequency
                                       : phy->link_frequency * 2;

The same pattern exists in max9296a_init_phy() in patch 17.

I've tested the full series (backported to 6.6) with the above fix on
SA8775P + MAX96724 + MAX96717 with C-PHY 3-trio @ 700MHz.

Tested-by: Cory Keitz <ckeitz@amazon.com>