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Sat, 7 Mar 2026 17:03:09 +0000 Received: from localhost (10.119.200.184) by EX19D001UWA001.ant.amazon.com (10.13.138.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.2562.37; Sat, 7 Mar 2026 17:03:09 +0000 Date: Sat, 7 Mar 2026 09:03:08 -0800 From: Cory Keitz To: CC: Tomi Valkeinen , "Mauro Carvalho Chehab" , Sakari Ailus , Laurent Pinchart , Julien Massot , Rob Herring , Niklas =?utf-8?Q?S=C3=B6derlund?= , "Greg Kroah-Hartman" , , , , , , , Cosmin Tanislav , Niklas =?utf-8?Q?S=C3=B6derlund?= Subject: Re: [PATCH RESEND v8 16/21] media: i2c: maxim-serdes: add MAX96724 driver Message-ID: References: <20251208-gmsl2-3_serdes-v8-0-7b8d457e2e04@analog.com> <20251208-gmsl2-3_serdes-v8-16-7b8d457e2e04@analog.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline In-Reply-To: <20251208-gmsl2-3_serdes-v8-16-7b8d457e2e04@analog.com> X-ClientProxiedBy: EX19D041UWA003.ant.amazon.com (10.13.139.105) To EX19D001UWA001.ant.amazon.com (10.13.138.214) On Mon, Dec 08, 2025 at 04:13:08PM +0200, Dumitru Ceclan via B4 Relay wrote: > +static int max96724_init_phy(struct max_des *des, struct max_des_phy *phy) > +{ > + struct max96724_priv *priv = des_to_priv(des); > + bool is_cphy = phy->bus_type == V4L2_MBUS_CSI2_CPHY; > + unsigned int num_data_lanes = phy->mipi.num_data_lanes; > + unsigned int dpll_freq = phy->link_frequency * 2; This unconditionally doubles the link frequency for the DPLL, which is correct for D-PHY (DDR clocking) but incorrect for C-PHY. Per the MAX96724 User Guide: D-PHY: "Clock freq is half; Data rate is equivalent bps/lane." e.g. 00010 = 200MHz DPLL, 200Mbps/lane data rate. C-PHY: "2.28bits/symbol." e.g. 00010 = 200MHz DPLL, 456Mbps/lane data rate. For C-PHY the DPLL value equals the symbol rate, which is the link frequency directly. Should be: unsigned int dpll_freq = is_cphy ? phy->link_frequency : phy->link_frequency * 2; The same pattern exists in max9296a_init_phy() in patch 17. I've tested the full series (backported to 6.6) with the above fix on SA8775P + MAX96724 + MAX96717 with C-PHY 3-trio @ 700MHz. Tested-by: Cory Keitz