* [PATCH v4 1/3] media: dt-bindings: Add qcom,sm6150-camss
2026-01-12 8:04 [PATCH v4 0/3] media: qcom: camss: Add sm6150 camss support Wenmeng Liu
@ 2026-01-12 8:04 ` Wenmeng Liu
2026-01-12 8:04 ` [PATCH v4 2/3] media: qcom: camss: add support for SM6150 camss Wenmeng Liu
2026-01-12 8:04 ` [PATCH v4 3/3] arm64: dts: qcom: talos: Add camss node Wenmeng Liu
2 siblings, 0 replies; 6+ messages in thread
From: Wenmeng Liu @ 2026-01-12 8:04 UTC (permalink / raw)
To: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Wenmeng Liu, Bjorn Andersson,
Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel,
Krzysztof Kozlowski
Add bindings for the Camera Subsystem on the SM6150 SoC
The SM6150 platform provides:
- 2 x VFE (version 170), each with 3 RDI
- 1 x VFE Lite (version 170), each with 4 RDI
- 2 x CSID (version 170)
- 1 x CSID Lite (version 170)
- 3 x CSIPHY (version 2.0.0)
- 1 x BPS (Bayer Processing Segment)
- 1 x ICP (Imaging Control Processor)
- 1 x IPE (Image Postprocessing Engine)
- 1 x JPEG Encoder/Decoder
- 1 x LRME (Low Resolution Motion Estimation)
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
.../bindings/media/qcom,sm6150-camss.yaml | 439 +++++++++++++++++++++
1 file changed, 439 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,sm6150-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm6150-camss.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..ba7b0acb9128b5dc9b09a863b4be0ed630e75d69
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,sm6150-camss.yaml
@@ -0,0 +1,439 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sm6150-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6150 Camera Subsystem (CAMSS)
+
+maintainers:
+ - Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
+
+description:
+ This binding describes the camera subsystem hardware found on SM6150
+ Qualcomm SoCs. It includes submodules such as CSIPHY (CSI Physical layer)
+ and CSID (CSI Decoder), which comply with the MIPI CSI2 protocol.
+
+ The subsystem also integrates a set of real-time image processing engines
+ and their associated configuration modules, as well as non-real-time engines.
+
+properties:
+ compatible:
+ const: qcom,sm6150-camss
+
+ reg:
+ items:
+ - description: Registers for CSID 0
+ - description: Registers for CSID 1
+ - description: Registers for CSID Lite
+ - description: Registers for CSIPHY 0
+ - description: Registers for CSIPHY 1
+ - description: Registers for CSIPHY 2
+ - description: Registers for VFE 0
+ - description: Registers for VFE 1
+ - description: Registers for VFE Lite
+ - description: Registers for BPS (Bayer Processing Segment)
+ - description: Registers for CAMNOC
+ - description: Registers for CPAS CDM
+ - description: Registers for CPAS TOP
+ - description: Registers for ICP (Imaging Control Processor) CSR (Control and Status Registers)
+ - description: Registers for ICP QGIC (Qualcomm Generic Interrupt Controller)
+ - description: Registers for ICP SIERRA ((A5 subsystem communication))
+ - description: Registers for IPE (Image Postprocessing Engine) 0
+ - description: Registers for JPEG DMA
+ - description: Registers for JPEG ENC
+ - description: Registers for LRME (Low Resolution Motion Estimation)
+
+ reg-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid_lite
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: vfe0
+ - const: vfe1
+ - const: vfe_lite
+ - const: bps
+ - const: camnoc
+ - const: cpas_cdm
+ - const: cpas_top
+ - const: icp_csr
+ - const: icp_qgic
+ - const: icp_sierra
+ - const: ipe0
+ - const: jpeg_dma
+ - const: jpeg_enc
+ - const: lrme
+
+ clocks:
+ maxItems: 33
+
+ clock-names:
+ items:
+ - const: gcc_ahb
+ - const: gcc_axi_hf
+ - const: camnoc_axi
+ - const: cpas_ahb
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: csiphy2
+ - const: csiphy2_timer
+ - const: soc_ahb
+ - const: vfe0
+ - const: vfe0_axi
+ - const: vfe0_cphy_rx
+ - const: vfe0_csid
+ - const: vfe1
+ - const: vfe1_axi
+ - const: vfe1_cphy_rx
+ - const: vfe1_csid
+ - const: vfe_lite
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+ - const: bps
+ - const: bps_ahb
+ - const: bps_axi
+ - const: bps_areg
+ - const: icp
+ - const: ipe0
+ - const: ipe0_ahb
+ - const: ipe0_areg
+ - const: ipe0_axi
+ - const: jpeg
+ - const: lrme
+
+ interrupts:
+ maxItems: 15
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid_lite
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: vfe0
+ - const: vfe1
+ - const: vfe_lite
+ - const: camnoc
+ - const: cdm
+ - const: icp
+ - const: jpeg_dma
+ - const: jpeg_enc
+ - const: lrme
+
+ interconnects:
+ maxItems: 4
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_0
+ - const: hf_1
+ - const: sf_mnoc
+
+ iommus:
+ items:
+ - description: Camera IFE 0 non-protected stream
+ - description: Camera IFE 1 non-protected stream
+ - description: Camera IFE 3 non-protected stream
+ - description: Camera CDM non-protected stream
+ - description: Camera LRME read non-protected stream
+ - description: Camera IPE 0 read non-protected stream
+ - description: Camera BPS read non-protected stream
+ - description: Camera IPE 0 write non-protected stream
+ - description: Camera BPS write non-protected stream
+ - description: Camera LRME write non-protected stream
+ - description: Camera JPEG read non-protected stream
+ - description: Camera JPEG write non-protected stream
+ - description: Camera ICP stream
+
+ power-domains:
+ items:
+ - description:
+ IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description:
+ IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description:
+ Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
+ - description:
+ Titan BPS - Bayer Processing Segment, Global Distributed Switch Controller.
+ - description:
+ IPE GDSC - Image Postprocessing Engine, Global Distributed Switch Controller.
+
+ power-domain-names:
+ items:
+ - const: ife0
+ - const: ife1
+ - const: top
+ - const: bps
+ - const: ipe
+
+ vdd-csiphy-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSI PHYs.
+
+ vdd-csiphy-1p8-supply:
+ description:
+ Phandle to 1.8V regulator supply to CSI PHYs pll block.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ patternProperties:
+ "^port@[0-2]$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+
+ description:
+ Input port for receiving CSI data from a CSIPHY.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,qcs615-camcc.h>
+ #include <dt-bindings/clock/qcom,qcs615-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ camss: isp@acb3000 {
+ compatible = "qcom,sm6150-camss";
+
+ reg = <0x0 0x0acb3000 0x0 0x1000>,
+ <0x0 0x0acba000 0x0 0x1000>,
+ <0x0 0x0acc8000 0x0 0x1000>,
+ <0x0 0x0ac65000 0x0 0x1000>,
+ <0x0 0x0ac66000 0x0 0x1000>,
+ <0x0 0x0ac67000 0x0 0x1000>,
+ <0x0 0x0acaf000 0x0 0x4000>,
+ <0x0 0x0acb6000 0x0 0x4000>,
+ <0x0 0x0acc4000 0x0 0x4000>,
+ <0x0 0x0ac6f000 0x0 0x3000>,
+ <0x0 0x0ac42000 0x0 0x5000>,
+ <0x0 0x0ac48000 0x0 0x1000>,
+ <0x0 0x0ac40000 0x0 0x1000>,
+ <0x0 0x0ac18000 0x0 0x3000>,
+ <0x0 0x0ac00000 0x0 0x6000>,
+ <0x0 0x0ac10000 0x0 0x8000>,
+ <0x0 0x0ac87000 0x0 0x3000>,
+ <0x0 0x0ac52000 0x0 0x4000>,
+ <0x0 0x0ac4e000 0x0 0x4000>,
+ <0x0 0x0ac6b000 0x0 0x0a00>;
+ reg-names = "csid0",
+ "csid1",
+ "csid_lite",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite",
+ "bps",
+ "camnoc",
+ "cpas_cdm",
+ "cpas_top",
+ "icp_csr",
+ "icp_qgic",
+ "icp_sierra",
+ "ipe0",
+ "jpeg_dma",
+ "jpeg_enc",
+ "lrme";
+
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_SOC_AHB_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_0_CSID_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_AXI_CLK>,
+ <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_1_CSID_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_BPS_CLK>,
+ <&camcc CAM_CC_BPS_AHB_CLK>,
+ <&camcc CAM_CC_BPS_AXI_CLK>,
+ <&camcc CAM_CC_BPS_AREG_CLK>,
+ <&camcc CAM_CC_ICP_CLK>,
+ <&camcc CAM_CC_IPE_0_CLK>,
+ <&camcc CAM_CC_IPE_0_AHB_CLK>,
+ <&camcc CAM_CC_IPE_0_AREG_CLK>,
+ <&camcc CAM_CC_IPE_0_AXI_CLK>,
+ <&camcc CAM_CC_JPEG_CLK>,
+ <&camcc CAM_CC_LRME_CLK>;
+
+ clock-names = "gcc_ahb",
+ "gcc_axi_hf",
+ "camnoc_axi",
+ "cpas_ahb",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "soc_ahb",
+ "vfe0",
+ "vfe0_axi",
+ "vfe0_cphy_rx",
+ "vfe0_csid",
+ "vfe1",
+ "vfe1_axi",
+ "vfe1_cphy_rx",
+ "vfe1_csid",
+ "vfe_lite",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "bps",
+ "bps_ahb",
+ "bps_axi",
+ "bps_areg",
+ "icp",
+ "ipe0",
+ "ipe0_ahb",
+ "ipe0_areg",
+ "ipe0_axi",
+ "jpeg",
+ "lrme";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_HF1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_0",
+ "hf_1",
+ "sf_mnoc";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 476 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid_lite",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite",
+ "camnoc",
+ "cdm",
+ "icp",
+ "jpeg_dma",
+ "jpeg_enc",
+ "lrme";
+
+ iommus = <&apps_smmu 0x0820 0x40>,
+ <&apps_smmu 0x0840 0x00>,
+ <&apps_smmu 0x0860 0x40>,
+ <&apps_smmu 0x0c00 0x00>,
+ <&apps_smmu 0x0cc0 0x00>,
+ <&apps_smmu 0x0c80 0x00>,
+ <&apps_smmu 0x0ca0 0x00>,
+ <&apps_smmu 0x0d00 0x00>,
+ <&apps_smmu 0x0d20 0x00>,
+ <&apps_smmu 0x0d40 0x00>,
+ <&apps_smmu 0x0d80 0x20>,
+ <&apps_smmu 0x0da0 0x20>,
+ <&apps_smmu 0x0de2 0x00>;
+
+ power-domains = <&camcc IFE_0_GDSC>,
+ <&camcc IFE_1_GDSC>,
+ <&camcc TITAN_TOP_GDSC>,
+ <&camcc BPS_GDSC>,
+ <&camcc IPE_0_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "top",
+ "bps",
+ "ipe";
+
+ vdd-csiphy-1p2-supply = <&vreg_l11a_1p2>;
+ vdd-csiphy-1p8-supply = <&vreg_l12a_1p8>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ csiphy_ep0: endpoint {
+ data-lanes = <0 1>;
+ remote-endpoint = <&sensor_ep>;
+ };
+ };
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v4 2/3] media: qcom: camss: add support for SM6150 camss
2026-01-12 8:04 [PATCH v4 0/3] media: qcom: camss: Add sm6150 camss support Wenmeng Liu
2026-01-12 8:04 ` [PATCH v4 1/3] media: dt-bindings: Add qcom,sm6150-camss Wenmeng Liu
@ 2026-01-12 8:04 ` Wenmeng Liu
2026-01-12 8:04 ` [PATCH v4 3/3] arm64: dts: qcom: talos: Add camss node Wenmeng Liu
2 siblings, 0 replies; 6+ messages in thread
From: Wenmeng Liu @ 2026-01-12 8:04 UTC (permalink / raw)
To: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Wenmeng Liu, Bjorn Andersson,
Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel
The camera subsystem for SM6150 which is based on Spectra 230.
For SM6150:
- VFE and CSID version: 170 (vfe170, csid170)
- CSIPHY version: csiphy-v2.0.1 (14nm)
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
.../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 2 +
drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
drivers/media/platform/qcom/camss/camss.c | 198 +++++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
4 files changed, 203 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index 619abbf6078130bb6f036eac3ab369cdf4841054..0bd9e1f0cd82347dc6b9d11b2d3179e4c95aa287 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -1004,6 +1004,7 @@ static bool csiphy_is_gen2(u32 version)
switch (version) {
case CAMSS_2290:
+ case CAMSS_6150:
case CAMSS_7280:
case CAMSS_8250:
case CAMSS_8280XP:
@@ -1093,6 +1094,7 @@ static int csiphy_init(struct csiphy_device *csiphy)
regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
break;
case CAMSS_2290:
+ case CAMSS_6150:
regs->lane_regs = &lane_regs_qcm2290[0];
regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
break;
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 9c7ad8aa405888ccea283ffd5cb038fc5bc4ee79..5baf0e3d4bc461df28d8dcf97a98dec04fa17ceb 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -342,6 +342,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
break;
case CAMSS_660:
case CAMSS_2290:
+ case CAMSS_6150:
case CAMSS_7280:
case CAMSS_8x96:
case CAMSS_8250:
@@ -2001,6 +2002,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
int ret = 8;
switch (vfe->camss->res->version) {
+ case CAMSS_6150:
case CAMSS_7280:
case CAMSS_8250:
case CAMSS_8280XP:
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 6cfb71fcd861c7930f0f4cb952a017e30aa3e396..e15d3b7cbdb40ca2dd8e7421bc4f3bb9f05b802d 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -1519,6 +1519,190 @@ static const struct camss_subdev_resources vfe_res_845[] = {
}
};
+static const struct camss_subdev_resources csiphy_res_sm6150[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = {
+ { .supply = "vdd-csiphy-1p2", .init_load_uA = 35000 },
+ { .supply = "vdd-csiphy-1p8", .init_load_uA = 5000 }
+ },
+ .clock = { "csiphy0", "csiphy0_timer" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 269333333 } },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .id = 0,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY1 */
+ {
+ .regulators = {
+ { .supply = "vdd-csiphy-1p2", .init_load_uA = 35000 },
+ { .supply = "vdd-csiphy-1p8", .init_load_uA = 5000 }
+ },
+ .clock = { "csiphy1", "csiphy1_timer" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 269333333 } },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .id = 1,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY2 */
+ {
+ .regulators = {
+ { .supply = "vdd-csiphy-1p2", .init_load_uA = 35000 },
+ { .supply = "vdd-csiphy-1p8", .init_load_uA = 5000 }
+ },
+ .clock = { "csiphy2", "csiphy2_timer" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 269333333 } },
+ .reg = { "csiphy2" },
+ .interrupt = { "csiphy2" },
+ .csiphy = {
+ .id = 2,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+};
+
+static const struct camss_subdev_resources csid_res_sm6150[] = {
+ /* CSID0 */
+ {
+ .regulators = {},
+ .clock = { "vfe0_cphy_rx", "vfe0_csid" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 320000000, 540000000 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .is_lite = false,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID1 */
+ {
+ .regulators = {},
+ .clock = { "vfe1_cphy_rx", "vfe1_csid" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 320000000, 540000000 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .is_lite = false,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID2 */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite_cphy_rx", "vfe_lite_csid" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 320000000, 540000000 } },
+ .reg = { "csid_lite" },
+ .interrupt = { "csid_lite" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+};
+
+static const struct camss_subdev_resources vfe_res_sm6150[] = {
+ /* VFE0 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "camnoc_axi", "cpas_ahb", "soc_ahb",
+ "vfe0", "vfe0_axi"},
+ .clock_rate = { { 0 },
+ { 0 },
+ { 80000000 },
+ { 37500000, 40000000 },
+ { 360000000, 432000000, 540000000, 600000000 },
+ { 265000000, 426000000 } },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .has_pd = true,
+ .pd_name = "ife0",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE1 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "camnoc_axi", "cpas_ahb", "soc_ahb",
+ "vfe1", "vfe1_axi"},
+ .clock_rate = { { 0 },
+ { 0 },
+ { 80000000 },
+ { 37500000, 40000000 },
+ { 360000000, 432000000, 540000000, 600000000 },
+ { 265000000, 426000000 } },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .has_pd = true,
+ .pd_name = "ife1",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE2 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "camnoc_axi", "cpas_ahb", "soc_ahb",
+ "vfe_lite" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 80000000 },
+ { 37500000, 40000000 },
+ { 360000000, 432000000, 540000000, 600000000 } },
+ .reg = { "vfe_lite" },
+ .interrupt = { "vfe_lite" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+};
+
+static const struct resources_icc icc_res_sm6150[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 38400,
+ .icc_bw_tbl.peak = 76800,
+ },
+ {
+ .name = "hf_0",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_8250[] = {
/* CSIPHY0 */
{
@@ -5050,6 +5234,19 @@ static const struct camss_resources sdm845_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_845),
};
+static const struct camss_resources sm6150_resources = {
+ .version = CAMSS_6150,
+ .pd_name = "top",
+ .csiphy_res = csiphy_res_sm6150,
+ .csid_res = csid_res_sm6150,
+ .vfe_res = vfe_res_sm6150,
+ .icc_res = icc_res_sm6150,
+ .icc_path_num = ARRAY_SIZE(icc_res_sm6150),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_sm6150),
+ .csid_num = ARRAY_SIZE(csid_res_sm6150),
+ .vfe_num = ARRAY_SIZE(vfe_res_sm6150),
+};
+
static const struct camss_resources sm8250_resources = {
.version = CAMSS_8250,
.pd_name = "top",
@@ -5145,6 +5342,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
{ .compatible = "qcom,sdm670-camss", .data = &sdm670_resources },
{ .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
+ { .compatible = "qcom,sm6150-camss", .data = &sm6150_resources },
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index e34f06b4e1536129e6d1cd5b719d2c7df8e39a23..6d048414c919e963d6eb0cba2a287015cb25416f 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -80,6 +80,7 @@ enum pm_domain {
enum camss_version {
CAMSS_660,
CAMSS_2290,
+ CAMSS_6150,
CAMSS_7280,
CAMSS_8x16,
CAMSS_8x39,
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v4 3/3] arm64: dts: qcom: talos: Add camss node
2026-01-12 8:04 [PATCH v4 0/3] media: qcom: camss: Add sm6150 camss support Wenmeng Liu
2026-01-12 8:04 ` [PATCH v4 1/3] media: dt-bindings: Add qcom,sm6150-camss Wenmeng Liu
2026-01-12 8:04 ` [PATCH v4 2/3] media: qcom: camss: add support for SM6150 camss Wenmeng Liu
@ 2026-01-12 8:04 ` Wenmeng Liu
2026-03-24 3:07 ` Bjorn Andersson
2 siblings, 1 reply; 6+ messages in thread
From: Wenmeng Liu @ 2026-01-12 8:04 UTC (permalink / raw)
To: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Wenmeng Liu, Bjorn Andersson,
Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel
Add node for the SM6150 camera subsystem.
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/talos.dtsi | 200 ++++++++++++++++++++++++++++++++++++
1 file changed, 200 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index 8171ec482be054a6d2bc8afdd1a122fa4fc591a2..5e5b43441e8919d6afc5a457e61f8a49664db66a 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -3780,6 +3780,206 @@ videocc: clock-controller@ab00000 {
#power-domain-cells = <1>;
};
+ camss: isp@acb3000 {
+ compatible = "qcom,sm6150-camss";
+
+ reg = <0x0 0x0acb3000 0x0 0x1000>,
+ <0x0 0x0acba000 0x0 0x1000>,
+ <0x0 0x0acc8000 0x0 0x1000>,
+ <0x0 0x0ac65000 0x0 0x1000>,
+ <0x0 0x0ac66000 0x0 0x1000>,
+ <0x0 0x0ac67000 0x0 0x1000>,
+ <0x0 0x0acaf000 0x0 0x4000>,
+ <0x0 0x0acb6000 0x0 0x4000>,
+ <0x0 0x0acc4000 0x0 0x4000>,
+ <0x0 0x0ac6f000 0x0 0x3000>,
+ <0x0 0x0ac42000 0x0 0x5000>,
+ <0x0 0x0ac48000 0x0 0x1000>,
+ <0x0 0x0ac40000 0x0 0x1000>,
+ <0x0 0x0ac18000 0x0 0x3000>,
+ <0x0 0x0ac00000 0x0 0x6000>,
+ <0x0 0x0ac10000 0x0 0x8000>,
+ <0x0 0x0ac87000 0x0 0x3000>,
+ <0x0 0x0ac52000 0x0 0x4000>,
+ <0x0 0x0ac4e000 0x0 0x4000>,
+ <0x0 0x0ac6b000 0x0 0x0a00>;
+ reg-names = "csid0",
+ "csid1",
+ "csid_lite",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite",
+ "bps",
+ "camnoc",
+ "cpas_cdm",
+ "cpas_top",
+ "icp_csr",
+ "icp_qgic",
+ "icp_sierra",
+ "ipe0",
+ "jpeg_dma",
+ "jpeg_enc",
+ "lrme";
+
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_SOC_AHB_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_0_CSID_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_AXI_CLK>,
+ <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_1_CSID_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_BPS_CLK>,
+ <&camcc CAM_CC_BPS_AHB_CLK>,
+ <&camcc CAM_CC_BPS_AXI_CLK>,
+ <&camcc CAM_CC_BPS_AREG_CLK>,
+ <&camcc CAM_CC_ICP_CLK>,
+ <&camcc CAM_CC_IPE_0_CLK>,
+ <&camcc CAM_CC_IPE_0_AHB_CLK>,
+ <&camcc CAM_CC_IPE_0_AREG_CLK>,
+ <&camcc CAM_CC_IPE_0_AXI_CLK>,
+ <&camcc CAM_CC_JPEG_CLK>,
+ <&camcc CAM_CC_LRME_CLK>;
+ clock-names = "gcc_ahb",
+ "gcc_axi_hf",
+ "camnoc_axi",
+ "cpas_ahb",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "soc_ahb",
+ "vfe0",
+ "vfe0_axi",
+ "vfe0_cphy_rx",
+ "vfe0_csid",
+ "vfe1",
+ "vfe1_axi",
+ "vfe1_cphy_rx",
+ "vfe1_csid",
+ "vfe_lite",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "bps",
+ "bps_ahb",
+ "bps_axi",
+ "bps_areg",
+ "icp",
+ "ipe0",
+ "ipe0_ahb",
+ "ipe0_areg",
+ "ipe0_axi",
+ "jpeg",
+ "lrme";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_HF1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_0",
+ "hf_1",
+ "sf_mnoc";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 476 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid_lite",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite",
+ "camnoc",
+ "cdm",
+ "icp",
+ "jpeg_dma",
+ "jpeg_enc",
+ "lrme";
+
+ iommus = <&apps_smmu 0x0820 0x40>,
+ <&apps_smmu 0x0840 0x00>,
+ <&apps_smmu 0x0860 0x40>,
+ <&apps_smmu 0x0c00 0x00>,
+ <&apps_smmu 0x0cc0 0x00>,
+ <&apps_smmu 0x0c80 0x00>,
+ <&apps_smmu 0x0ca0 0x00>,
+ <&apps_smmu 0x0d00 0x00>,
+ <&apps_smmu 0x0d20 0x00>,
+ <&apps_smmu 0x0d40 0x00>,
+ <&apps_smmu 0x0d80 0x20>,
+ <&apps_smmu 0x0da0 0x20>,
+ <&apps_smmu 0x0de2 0x00>;
+
+ power-domains = <&camcc IFE_0_GDSC>,
+ <&camcc IFE_1_GDSC>,
+ <&camcc TITAN_TOP_GDSC>,
+ <&camcc BPS_GDSC>,
+ <&camcc IPE_0_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "top",
+ "bps",
+ "ipe";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ };
+ };
+ };
+
camcc: clock-controller@ad00000 {
compatible = "qcom,qcs615-camcc";
reg = <0 0x0ad00000 0 0x10000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v4 3/3] arm64: dts: qcom: talos: Add camss node
2026-01-12 8:04 ` [PATCH v4 3/3] arm64: dts: qcom: talos: Add camss node Wenmeng Liu
@ 2026-03-24 3:07 ` Bjorn Andersson
2026-03-24 5:46 ` Wenmeng Liu
0 siblings, 1 reply; 6+ messages in thread
From: Bjorn Andersson @ 2026-03-24 3:07 UTC (permalink / raw)
To: Wenmeng Liu
Cc: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, linux-media,
linux-arm-msm, devicetree, linux-kernel
On Mon, Jan 12, 2026 at 04:04:54PM +0800, Wenmeng Liu wrote:
> Add node for the SM6150 camera subsystem.
>
> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
arch/arm64/boot/dts/qcom/qcs615-ride.dtb: isp@acb3000 (qcom,sm6150-camss) interrupts: [[0, 464, 1, 0], [466, 1, 0, 468], [1, 0, 477, 1], [0, 478, 1, 0], [479, 1, 0, 465], [1, 0, 467, 1], [0, 469, 1, 0], [459, 1, 0, 461], [1, 0, 463, 1], [0, 475, 1, 0], [474, 1, 0, 476], [1]] is too short
Regards,
Bjorn
> ---
> arch/arm64/boot/dts/qcom/talos.dtsi | 200 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 200 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
> index 8171ec482be054a6d2bc8afdd1a122fa4fc591a2..5e5b43441e8919d6afc5a457e61f8a49664db66a 100644
> --- a/arch/arm64/boot/dts/qcom/talos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/talos.dtsi
> @@ -3780,6 +3780,206 @@ videocc: clock-controller@ab00000 {
> #power-domain-cells = <1>;
> };
>
> + camss: isp@acb3000 {
> + compatible = "qcom,sm6150-camss";
> +
> + reg = <0x0 0x0acb3000 0x0 0x1000>,
> + <0x0 0x0acba000 0x0 0x1000>,
> + <0x0 0x0acc8000 0x0 0x1000>,
> + <0x0 0x0ac65000 0x0 0x1000>,
> + <0x0 0x0ac66000 0x0 0x1000>,
> + <0x0 0x0ac67000 0x0 0x1000>,
> + <0x0 0x0acaf000 0x0 0x4000>,
> + <0x0 0x0acb6000 0x0 0x4000>,
> + <0x0 0x0acc4000 0x0 0x4000>,
> + <0x0 0x0ac6f000 0x0 0x3000>,
> + <0x0 0x0ac42000 0x0 0x5000>,
> + <0x0 0x0ac48000 0x0 0x1000>,
> + <0x0 0x0ac40000 0x0 0x1000>,
> + <0x0 0x0ac18000 0x0 0x3000>,
> + <0x0 0x0ac00000 0x0 0x6000>,
> + <0x0 0x0ac10000 0x0 0x8000>,
> + <0x0 0x0ac87000 0x0 0x3000>,
> + <0x0 0x0ac52000 0x0 0x4000>,
> + <0x0 0x0ac4e000 0x0 0x4000>,
> + <0x0 0x0ac6b000 0x0 0x0a00>;
> + reg-names = "csid0",
> + "csid1",
> + "csid_lite",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "vfe0",
> + "vfe1",
> + "vfe_lite",
> + "bps",
> + "camnoc",
> + "cpas_cdm",
> + "cpas_top",
> + "icp_csr",
> + "icp_qgic",
> + "icp_sierra",
> + "ipe0",
> + "jpeg_dma",
> + "jpeg_enc",
> + "lrme";
> +
> + clocks = <&gcc GCC_CAMERA_AHB_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY1_CLK>,
> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY2_CLK>,
> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&camcc CAM_CC_SOC_AHB_CLK>,
> + <&camcc CAM_CC_IFE_0_CLK>,
> + <&camcc CAM_CC_IFE_0_AXI_CLK>,
> + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_0_CSID_CLK>,
> + <&camcc CAM_CC_IFE_1_CLK>,
> + <&camcc CAM_CC_IFE_1_AXI_CLK>,
> + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_1_CSID_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
> + <&camcc CAM_CC_BPS_CLK>,
> + <&camcc CAM_CC_BPS_AHB_CLK>,
> + <&camcc CAM_CC_BPS_AXI_CLK>,
> + <&camcc CAM_CC_BPS_AREG_CLK>,
> + <&camcc CAM_CC_ICP_CLK>,
> + <&camcc CAM_CC_IPE_0_CLK>,
> + <&camcc CAM_CC_IPE_0_AHB_CLK>,
> + <&camcc CAM_CC_IPE_0_AREG_CLK>,
> + <&camcc CAM_CC_IPE_0_AXI_CLK>,
> + <&camcc CAM_CC_JPEG_CLK>,
> + <&camcc CAM_CC_LRME_CLK>;
> + clock-names = "gcc_ahb",
> + "gcc_axi_hf",
> + "camnoc_axi",
> + "cpas_ahb",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "soc_ahb",
> + "vfe0",
> + "vfe0_axi",
> + "vfe0_cphy_rx",
> + "vfe0_csid",
> + "vfe1",
> + "vfe1_axi",
> + "vfe1_cphy_rx",
> + "vfe1_csid",
> + "vfe_lite",
> + "vfe_lite_cphy_rx",
> + "vfe_lite_csid",
> + "bps",
> + "bps_ahb",
> + "bps_axi",
> + "bps_areg",
> + "icp",
> + "ipe0",
> + "ipe0_ahb",
> + "ipe0_areg",
> + "ipe0_axi",
> + "jpeg",
> + "lrme";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mmss_noc MASTER_CAMNOC_HF0 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc MASTER_CAMNOC_HF1 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "ahb",
> + "hf_0",
> + "hf_1",
> + "sf_mnoc";
> +
> + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 476 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "csid0",
> + "csid1",
> + "csid_lite",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "vfe0",
> + "vfe1",
> + "vfe_lite",
> + "camnoc",
> + "cdm",
> + "icp",
> + "jpeg_dma",
> + "jpeg_enc",
> + "lrme";
> +
> + iommus = <&apps_smmu 0x0820 0x40>,
> + <&apps_smmu 0x0840 0x00>,
> + <&apps_smmu 0x0860 0x40>,
> + <&apps_smmu 0x0c00 0x00>,
> + <&apps_smmu 0x0cc0 0x00>,
> + <&apps_smmu 0x0c80 0x00>,
> + <&apps_smmu 0x0ca0 0x00>,
> + <&apps_smmu 0x0d00 0x00>,
> + <&apps_smmu 0x0d20 0x00>,
> + <&apps_smmu 0x0d40 0x00>,
> + <&apps_smmu 0x0d80 0x20>,
> + <&apps_smmu 0x0da0 0x20>,
> + <&apps_smmu 0x0de2 0x00>;
> +
> + power-domains = <&camcc IFE_0_GDSC>,
> + <&camcc IFE_1_GDSC>,
> + <&camcc TITAN_TOP_GDSC>,
> + <&camcc BPS_GDSC>,
> + <&camcc IPE_0_GDSC>;
> + power-domain-names = "ife0",
> + "ife1",
> + "top",
> + "bps",
> + "ipe";
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> +
> + port@2 {
> + reg = <2>;
> + };
> + };
> + };
> +
> camcc: clock-controller@ad00000 {
> compatible = "qcom,qcs615-camcc";
> reg = <0 0x0ad00000 0 0x10000>;
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v4 3/3] arm64: dts: qcom: talos: Add camss node
2026-03-24 3:07 ` Bjorn Andersson
@ 2026-03-24 5:46 ` Wenmeng Liu
0 siblings, 0 replies; 6+ messages in thread
From: Wenmeng Liu @ 2026-03-24 5:46 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, linux-media,
linux-arm-msm, devicetree, linux-kernel
On 3/24/2026 11:07 AM, Bjorn Andersson wrote:
> On Mon, Jan 12, 2026 at 04:04:54PM +0800, Wenmeng Liu wrote:
>> Add node for the SM6150 camera subsystem.
>>
>> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
>> Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
>> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
>
> arch/arm64/boot/dts/qcom/qcs615-ride.dtb: isp@acb3000 (qcom,sm6150-camss) interrupts: [[0, 464, 1, 0], [466, 1, 0, 468], [1, 0, 477, 1], [0, 478, 1, 0], [479, 1, 0, 465], [1, 0, 467, 1], [0, 469, 1, 0], [459, 1, 0, 461], [1, 0, 463, 1], [0, 475, 1, 0], [474, 1, 0, 476], [1]] is too short
>
> Regards,
> Bjorn
this is old version, v6 has been posted.
https://lore.kernel.org/all/2e13c91a-6d87-4c2b-8a98-0b58f97023ed@oss.qualcomm.com/
Thanks,
Wenmeng
^ permalink raw reply [flat|nested] 6+ messages in thread