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From: Andreas Helbech Kleist <andreaskleist@gmail.com>
To: bingbu.cao@intel.com, linux-media@vger.kernel.org,
	 sakari.ailus@linux.intel.com, laurent.pinchart@ideasonboard.com
Cc: andriy.shevchenko@linux.intel.com, hdegoede@redhat.com,
	 ilpo.jarvinen@linux.intel.com, claus.stovgaard@gmail.com,
	tfiga@chromium.org,  senozhatsky@chromium.org,
	tomi.valkeinen@ideasonboard.com,  bingbu.cao@linux.intel.com,
	tian.shu.qiu@intel.com, hongju.wang@intel.com
Subject: Re: [PATCH v2 05/15] media: intel/ipu6: add IPU6 DMA mapping API and MMU table
Date: Wed, 06 Dec 2023 15:53:01 +0100	[thread overview]
Message-ID: <accabcd74cfd4017758965fd6ed6453018e5fbd8.camel@gmail.com> (raw)
In-Reply-To: <20231024112924.3934228-6-bingbu.cao@intel.com>

Hi,

On Tue, 2023-10-24 at 19:29 +0800, bingbu.cao@intel.com wrote:
> From: Bingbu Cao <bingbu.cao@intel.com>
> 
> he Intel IPU6 has an internal microcontroller (scalar processor, SP)
> which
> is used to execute the firmware. The SP can access IPU internal
> memory and
> map system DRAM to its an internal 32-bit virtual address space.
> 
> This patch adds a driver for the IPU MMU and a DMA mapping
> implementation
> using the internal MMU. The system IOMMU may be used besides the IPU
> MMU.
> 
> Signed-off-by: Bingbu Cao <bingbu.cao@intel.com>
> ---
>  drivers/media/pci/intel/ipu6/ipu6-dma.c | 491 ++++++++++++++
>  drivers/media/pci/intel/ipu6/ipu6-dma.h |  20 +
>  drivers/media/pci/intel/ipu6/ipu6-mmu.c | 828
> ++++++++++++++++++++++++
>  drivers/media/pci/intel/ipu6/ipu6-mmu.h |  67 ++
>  4 files changed, 1406 insertions(+)
>  create mode 100644 drivers/media/pci/intel/ipu6/ipu6-dma.c
>  create mode 100644 drivers/media/pci/intel/ipu6/ipu6-dma.h
>  create mode 100644 drivers/media/pci/intel/ipu6/ipu6-mmu.c
>  create mode 100644 drivers/media/pci/intel/ipu6/ipu6-mmu.h
...

> +++ b/drivers/media/pci/intel/ipu6/ipu6-mmu.c
...
> +static struct ipu6_mmu_info *ipu6_mmu_alloc(struct ipu6_device *isp)
> +{
> +       struct ipu6_mmu_info *mmu_info;
> +       int ret;
> +
> +       mmu_info = kzalloc(sizeof(*mmu_info), GFP_KERNEL);
> +       if (!mmu_info)
> +               return NULL;
> +
> +       mmu_info->aperture_start = 0;
> +       mmu_info->aperture_end = DMA_BIT_MASK(isp->secure_mode ?
> +                                             IPU6_MMU_ADDR_BITS :
> +                                            
> IPU6_MMU_ADDR_BITS_NON_SECURE);
> +       mmu_info->pgsize_bitmap = SZ_4K;
> +       mmu_info->dev = &isp->pdev->dev;
> +
> +       ret = get_dummy_page(mmu_info);
> +       if (ret)
> +               goto err_free_info;
> +
> +       ret = alloc_dummy_l2_pt(mmu_info);
> +       if (ret)
> +               goto err_free_dummy_page;
> +
> +       mmu_info->l2_pts = vzalloc(ISP_L2PT_PTES * sizeof(*mmu_info-
> >l2_pts));
> +       if (!mmu_info->l2_pts)
> +               goto err_free_dummy_l2_pt;
> +
> +       /*
> +        * We always map the L1 page table (a single page as well as
> +        * the L2 page tables).
> +        */
> +       mmu_info->l1_pt = alloc_l1_pt(mmu_info);
> +       if (!mmu_info->l1_pt)
> +               goto err_free_l2_pts;
> +
> +       spin_lock_init(&mmu_info->lock);
> +
> +       dev_dbg(mmu_info->dev, "domain initialised\n");
> +
> +       return mmu_info;
> +
> +err_free_l2_pts:
> +       vfree(mmu_info->l2_pts);
> +err_free_dummy_l2_pt:
> +       free_dummy_l2_pt(mmu_info);
> +err_free_dummy_page:
> +       free_dummy_page(mmu_info);
> +err_free_info:
> +       kfree(mmu_info);
> +
> +       return NULL;
> +}

...


> +static void ipu6_mmu_destroy(struct ipu6_mmu *mmu)
> +{
> +       struct ipu6_dma_mapping *dmap = mmu->dmap;
> +       struct ipu6_mmu_info *mmu_info = dmap->mmu_info;
> +       struct iova *iova;
> +       u32 l1_idx;
> +
> +       if (mmu->iova_trash_page) {
> +               iova = find_iova(&dmap->iovad, PHYS_PFN(mmu-
> >iova_trash_page));
> +               if (iova) {
> +                       /* unmap and free the trash buffer iova */
> +                       ipu6_mmu_unmap(mmu_info, PFN_PHYS(iova-
> >pfn_lo),
> +                                      PFN_PHYS(iova_size(iova)));
> +                       __free_iova(&dmap->iovad, iova);
> +               } else {
> +                       dev_err(mmu->dev, "trash buffer iova not
> found.\n");
> +               }
> +
> +               mmu->iova_trash_page = 0;
> +               dma_unmap_page(mmu_info->dev, mmu->pci_trash_page,
> +                              PAGE_SIZE, DMA_BIDIRECTIONAL);
> +               mmu->pci_trash_page = 0;
> +               __free_page(mmu->trash_page);
> +       }
> +
> +       for (l1_idx = 0; l1_idx < ISP_L1PT_PTES; l1_idx++) {
> +               if (mmu_info->l1_pt[l1_idx] != mmu_info-
> >dummy_l2_pteval) {
> +                       dma_unmap_single(mmu_info->dev,
> +                                        TBL_PHYS_ADDR(mmu_info-
> >l1_pt[l1_idx]),
> +                                        PAGE_SIZE,
> DMA_BIDIRECTIONAL);
> +                       free_page((unsigned long)mmu_info-
> >l2_pts[l1_idx]);
> +               }
> +       }
> +
> +       free_dummy_page(mmu_info);
> +       dma_unmap_single(mmu_info->dev, TBL_PHYS_ADDR(mmu_info-
> >l1_pt_dma),
> +                        PAGE_SIZE, DMA_BIDIRECTIONAL);
> +       free_page((unsigned long)mmu_info->dummy_l2_pt);
> +       free_page((unsigned long)mmu_info->l1_pt);
> +       kfree(mmu_info);
> +}

mmu_info->l2_pts is leaked here. It is allocated in ipu6_mmu_alloc and
freed in the error path of that function along with the other stuff you
free here, but not anywhere else.

/Andreas

  reply	other threads:[~2023-12-06 14:53 UTC|newest]

Thread overview: 86+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-24 11:29 [PATCH v2 00/15] Intel IPU6 and IPU6 input system drivers bingbu.cao
2023-10-24 11:29 ` [PATCH v2 01/15] media: intel/ipu6: add Intel IPU6 PCI device driver bingbu.cao
2023-10-25 12:39   ` Andreas Helbech Kleist
2023-10-25 20:03     ` Andy Shevchenko
2023-11-05 14:43   ` Hans de Goede
2023-11-06  8:55     ` Bingbu Cao
2023-11-08 11:25   ` Hans de Goede
2023-11-08 13:24     ` Andy Shevchenko
2023-11-08 14:10     ` Andreas Helbech Kleist
2023-11-08 14:18       ` Cao, Bingbu
2023-11-17 18:43       ` Hans de Goede
2023-11-17 21:18         ` Andy Shevchenko
2023-11-20  3:54           ` Bingbu Cao
2023-11-23  9:17   ` Andreas Helbech Kleist
2023-10-24 11:29 ` [PATCH v2 02/15] media: intel/ipu6: add IPU auxiliary devices bingbu.cao
2023-10-24 12:58   ` Andy Shevchenko
2023-10-25  7:14     ` Bingbu Cao
2023-10-25  8:35       ` Hans de Goede
2023-10-25 19:57       ` Andy Shevchenko
2023-10-26  3:04         ` Bingbu Cao
2023-10-24 11:29 ` [PATCH v2 03/15] media: intel/ipu6: add IPU6 buttress interface driver bingbu.cao
2024-01-03  9:22   ` Andreas Helbech Kleist
2024-01-03 10:49     ` Laurent Pinchart
2024-01-03 13:33       ` Bingbu Cao
2024-01-03 14:01         ` Laurent Pinchart
2024-01-03 13:11     ` Bingbu Cao
2024-01-03 13:18       ` Bingbu Cao
2024-01-08 10:27         ` Andreas Helbech Kleist
2023-10-24 11:29 ` [PATCH v2 04/15] media: intel/ipu6: CPD parsing for get firmware components bingbu.cao
2023-10-24 11:29 ` [PATCH v2 05/15] media: intel/ipu6: add IPU6 DMA mapping API and MMU table bingbu.cao
2023-12-06 14:53   ` Andreas Helbech Kleist [this message]
2023-10-24 11:29 ` [PATCH v2 06/15] media: intel/ipu6: add syscom interfaces between firmware and driver bingbu.cao
2023-11-23  9:33   ` Andreas Helbech Kleist
2023-12-28  6:39     ` Bingbu Cao
2024-01-03  9:25       ` Andreas Helbech Kleist
2024-01-08  4:19         ` Bingbu Cao
2023-10-24 11:29 ` [PATCH v2 07/15] media: intel/ipu6: input system ABI " bingbu.cao
2023-10-24 11:29 ` [PATCH v2 08/15] media: intel/ipu6: add IPU6 CSI2 receiver v4l2 sub-device bingbu.cao
2023-11-08 11:25   ` Andreas Helbech Kleist
2023-11-08 14:50     ` Cao, Bingbu
2023-11-08 14:51       ` Bingbu Cao
2023-11-08 15:00       ` Andreas Helbech Kleist
2023-11-08 15:32         ` andriy.shevchenko
2023-11-09  1:48           ` Bingbu Cao
2023-10-24 11:29 ` [PATCH v2 09/15] media: intel/ipu6: add the CSI2 DPHY implementation bingbu.cao
2023-10-24 11:29 ` [PATCH v2 10/15] media: intel/ipu6: add input system driver bingbu.cao
2023-11-23  9:37   ` Andreas Helbech Kleist
2024-01-09 13:52   ` Andreas Helbech Kleist
2024-01-10 12:47   ` Andreas Helbech Kleist
2023-10-24 11:29 ` [PATCH v2 11/15] media: intel/ipu6: input system video capture nodes bingbu.cao
2023-11-05 16:59   ` Hans de Goede
2023-11-06  9:18     ` Bingbu Cao
2023-11-06 11:17       ` Andy Shevchenko
2023-12-05  9:15         ` Bingbu Cao
2024-01-09 13:35   ` Andreas Helbech Kleist
2023-10-24 11:29 ` [PATCH v2 12/15] media: add Kconfig and Makefile for IPU6 bingbu.cao
2023-10-24 13:04   ` Andy Shevchenko
2023-10-25  8:43     ` Bingbu Cao
2023-10-25 20:00       ` Andy Shevchenko
2023-10-25 12:21     ` Sakari Ailus
2023-10-25 20:01       ` Andy Shevchenko
2023-10-24 11:29 ` [PATCH v2 13/15] MAINTAINERS: add maintainers for Intel IPU6 input system driver bingbu.cao
2023-10-24 11:29 ` [PATCH v2 14/15] Documentation: add Intel IPU6 ISYS driver admin-guide doc bingbu.cao
2023-10-25 12:15   ` Sakari Ailus
2024-01-08  3:51     ` Bingbu Cao
2024-01-08  9:14       ` Sakari Ailus
2024-01-09  6:34         ` Bingbu Cao
2024-01-09  8:55           ` Sakari Ailus
2024-01-09 11:00             ` Bingbu Cao
2023-10-24 11:29 ` [PATCH v2 15/15] Documentation: add documentation of Intel IPU6 driver and hardware overview bingbu.cao
2023-10-25 12:09   ` Sakari Ailus
2023-10-26  3:38     ` Bingbu Cao
2023-10-26  5:27       ` Sakari Ailus
2023-11-08 11:59 ` [PATCH v2 00/15] Intel IPU6 and IPU6 input system drivers Hans de Goede
2023-11-08 14:31   ` Cao, Bingbu
2023-11-08 15:15     ` Hans de Goede
2023-11-10 12:04   ` Hans de Goede
2023-11-13 10:37     ` Bingbu Cao
2023-12-04 16:35   ` Hans de Goede
2023-12-04 16:49     ` Andy Shevchenko
2024-01-08  4:07   ` Bingbu Cao
2024-01-08 14:23     ` Hans de Goede
2024-01-09  3:51       ` Bingbu Cao
2024-01-15 13:13         ` Hans de Goede
2024-02-07  7:00 ` Sakari Ailus
2024-02-14  9:28   ` Sakari Ailus

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