Re: [PATCH 1/1] media: Documentation: Improve PIXEL_RATE control documentation

[Jacopo Mondi <jacopo.mondi@ideasonboard.com>]

Hi Sakari

On Tue, Apr 14, 2026 at 01:35:59PM +0300, Sakari Ailus wrote:
> Document explicitly that the PIXEL_RATE control reflects the actual
> frequency at which the pixels are read in the pixel array. It is thus
> orthogonal to analogue binning.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
>  .../userspace-api/media/v4l/ext-ctrls-image-process.rst      | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-image-process.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-image-process.rst
> index 6d516f041ca2..8616bcd67270 100644
> --- a/Documentation/userspace-api/media/v4l/ext-ctrls-image-process.rst
> +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-image-process.rst
> @@ -41,6 +41,11 @@ Image Process Control IDs
>      The configuration of the frame rate is performed by selecting the desired
>      horizontal and vertical blanking. The unit of this control is Hz.
>
> +    Note that this control isn't affected by analogue binning as the pixels are
> +    still being read at the same frequency as without analogue binning, only
> +    what is being read is different (a single pixel value vs. a binned pixel
> +    value based on the values of two or more pixels).
> +

This breaks the model implemented to support "special" (aka analogue
?) binning mode on imx219 where we double the pixel rate to express an
higher frame rate and halve the blanking values before writing them to
registers

I guess we have to keep this mode working not to break existing
userspace, also because it's the only way we can have it working
without the introduction of the FLL and LLP controls.

With the new model and FLL and LLP controls, I presume analog binning
would require userspace to program halved FLL and LLP values ?

Currently in your proposal of V4L2_CID_BINNING_FACTORS it doesn't seem
there is a way to distinguish between  a digital and an analogue
binning mode, they're both 2x2 so I guess it's the driver that has to
realize that if FLL and LLP are smaller the [output width + blank] it
has to activate the analogue binning mode ?


>  ``V4L2_CID_TEST_PATTERN (menu)``
>      Some capture/display/sensor devices have the capability to generate
>      test pattern images. These hardware specific test patterns can be
> --
> 2.47.3
>