Re: [PATCH v2 04/15] media: i2c: os05b10: split common and mode-specific init registers

[Mehdi Djait <mehdi.djait@linux.intel.com>]

Hi Tarang,

On Wed, Mar 25, 2026 at 05:13:50PM +0530, Tarang Raval wrote:
> Separate common initialization registers from mode-specific settings.
> Move resolution-dependent registers into a per-mode register list and
> program them during stream enable.
> 
> Signed-off-by: Tarang Raval <tarang.raval@siliconsignals.io>
> ---
>  drivers/media/i2c/os05b10.c | 118 ++++++++++++++++++++++--------------
>  1 file changed, 74 insertions(+), 44 deletions(-)
> 
> diff --git a/drivers/media/i2c/os05b10.c b/drivers/media/i2c/os05b10.c
> index 751494fdba6d..9499867ad40e 100644
> --- a/drivers/media/i2c/os05b10.c
> +++ b/drivers/media/i2c/os05b10.c
> @@ -122,37 +122,34 @@ static const char * const os05b10_supply_name[] = {
>  };
>  
>  static const struct cci_reg_sequence os05b10_common_regs[] = {
> -	{ OS05B10_REG_PLL_CTRL_01, 0x44 },
> -	{ OS05B10_REG_PLL_CTRL_03, 0x02 },
> -	{ OS05B10_REG_PLL_CTRL_05, 0x32 },
> -	{ OS05B10_REG_PLL_CTRL_06, 0x00 },
> -	{ OS05B10_REG_PLL_CTRL_25, 0x3b },
> +	{ OS05B10_REG_PLL_CTRL_01,		0x44 },
> +	{ OS05B10_REG_PLL_CTRL_03,		0x02 },
> +	{ OS05B10_REG_PLL_CTRL_05,		0x32 },
> +	{ OS05B10_REG_PLL_CTRL_06,		0x00 },
> +	{ OS05B10_REG_PLL_CTRL_25,		0x3b },
> +	{ OS05B10_REG_MIPI_SC_CTRL,		0x72 },
> +	{ OS05B10_REG_MIPI_SC_CTRL_1,		0x01 },
> +	{ OS05B10_REG_DIGITAL_GAIN,		0x0400 },
> +	{ OS05B10_REG_ANALOG_GAIN_SHORT,	0x0080 },
> +	{ OS05B10_REG_DIGITAL_GAIN_SHORT,	0x0400 },
> +	{ OS05B10_REG_EXPOSURE_SHORT,		0x000020 },

The changes above seem to be more cosmetic and are not part of this
patch. the register values are also tab aligned not like the others
below

>  	{ CCI_REG8(0x3002), 0x21 },
> -	{ OS05B10_REG_MIPI_SC_CTRL, 0x72 },
>  	{ CCI_REG8(0x301e), 0xb4 },
>  	{ CCI_REG8(0x301f), 0xd0 },
>  	{ CCI_REG8(0x3021), 0x03 },
> -	{ OS05B10_REG_MIPI_SC_CTRL_1, 0x01 },
>  	{ CCI_REG8(0x3107), 0xa1 },
>  	{ CCI_REG8(0x3108), 0x7d },
>  	{ CCI_REG8(0x3109), 0xfc },
>  	{ CCI_REG8(0x3503), 0x88 },
> -	{ OS05B10_REG_DIGITAL_GAIN, 0x0400 },
> -	{ OS05B10_REG_ANALOG_GAIN_SHORT, 0x0080 },
> -	{ OS05B10_REG_DIGITAL_GAIN_SHORT, 0x0400 },
> -	{ OS05B10_REG_EXPOSURE_SHORT, 0x000020 },
>  	{ CCI_REG8(0x3600), 0x4d },
>  	{ CCI_REG8(0x3601), 0x08 },
> -	{ CCI_REG8(0x3610), 0x87 },
>  	{ CCI_REG8(0x3611), 0x24 },
>  	{ CCI_REG8(0x3614), 0x4c },
> -	{ CCI_REG8(0x3620), 0x0c },
>  	{ CCI_REG8(0x3632), 0x80 },
>  	{ CCI_REG8(0x3633), 0x00 },

--
Kind Regards
Mehdi Djait