Re: [PATCH v4 4/5] arm64: dts: qcom: purwa: Override Iris clocks and operating points

Dikshita Agarwal
2026-04-01T12:42:07Z

On 4/1/2026 3:54 PM, Wangao Wang wrote:
> The Iris block on X1P differs from SM8550/X1E in its clock configuration
> and requires a dedicated OPP table. The node inherited from the X1E cannot
> be reused directly, and the fallback compatible "qcom,sm8550-iris" cannot
> be applied.
>
> Override the inherited clocks, clock-names, and operating points, and
> replaces them with the X1P42100-specific definitions. A new OPP table
> is provided to support the correct performance levels on this platform.
>
> Depends-on: https://lore.kernel.org/all/20260331-purwa-videocc-camcc-v3-0-6daca180a4b1@oss.qualcomm.com/
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/purwa.dtsi | 50 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/purwa.dtsi b/arch/arm64/boot/dts/qcom/purwa.dtsi
> index 70e37fa91f5db83e66f9706b62637f6e18dffa89..c2f4457b83e193cff20120c50b53bf4c67e57239 100644
> --- a/arch/arm64/boot/dts/qcom/purwa.dtsi
> +++ b/arch/arm64/boot/dts/qcom/purwa.dtsi
> @@ -21,6 +21,7 @@
> /delete-node/ &cpu_pd11;
> /delete-node/ &gpu_opp_table;
> /delete-node/ &gpu_speed_bin;
> +/delete-node/ &iris_opp_table;
> /delete-node/ &pcie3_phy;
> /delete-node/ &thermal_aoss3;
> /delete-node/ &thermal_cpu2_0_btm;
> @@ -167,6 +168,55 @@ &gpucc {
> compatible = "qcom,x1p42100-gpucc";
> };
>
> +&iris {
> + compatible = "qcom,x1p42100-iris";
> +
> + clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
> + <&videocc VIDEO_CC_MVS0C_CLK>,
> + <&videocc VIDEO_CC_MVS0_CLK>,
> + <&videocc VIDEO_CC_MVS0_BSE_CLK>;
> + clock-names = "iface",
> + "core",
> + "vcodec0_core",
> + "vcodec0_bse";
> +
> + operating-points-v2 = <&iris_opp_table_x1p42100>;
> +
> + iris_opp_table_x1p42100: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-210000000 {
> + opp-hz = /bits/ 64 <210000000 105000000>;
> + required-opps = <&rpmhpd_opp_low_svs_d1>,
> + <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000 150000000>;
> + required-opps = <&rpmhpd_opp_low_svs_d1>,
> + <&rpmhpd_opp_svs>;
> + };
> +
> + opp-335000000 {
> + opp-hz = /bits/ 64 <335000000 167500000>;
> + required-opps = <&rpmhpd_opp_svs>,
> + <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-424000000 {
> + opp-hz = /bits/ 64 <424000000 212000000>;
> + required-opps = <&rpmhpd_opp_svs>,
> + <&rpmhpd_opp_nom>;
> + };
> +
> + opp-500000000 {
> + opp-hz = /bits/ 64 <500000000 250000000>;
> + required-opps = <&rpmhpd_opp_svs>,
> + <&rpmhpd_opp_turbo>;
> + };
> + };
> +};
> +
> /* PCIe3 has half the lanes compared to X1E80100 */
> &pcie3 {
> num-lanes = <4>;
>

Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>

Thanks,
Dikshita