From: khalasa@piap.pl (Krzysztof Hałasa)
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org, linux-media@vger.kernel.org
Subject: Re: Suspected cache coherency problem on V4L2 and AR7100 CPU
Date: Wed, 09 Oct 2013 08:53:20 +0200 [thread overview]
Message-ID: <m38uy37x5r.fsf@t19.piap.pl> (raw)
In-Reply-To: <20131008120727.GH1615@linux-mips.org> (Ralf Baechle's message of "Tue, 8 Oct 2013 14:07:27 +0200")
Ralf Baechle <ralf@linux-mips.org> writes:
> 16K is a silver bullet solution to all cache aliasing problems. So if
> your issue persists with 16K page size, it's not a cache aliasing issue.
> Aside there are generally performance gains from the bigger page size.
I wonder why isn't the issue present in other cases. Perhaps remapping
of a userspace address and accessing it with kseg0 isn't a frequent
operation.
Shouldn't we change the default page size (on affected CPUs) to 16 KB
then? Alternatively, we could flush/invalidate the cache when needed -
is it a viable option?
Thanks.
--
Krzysztof Halasa
Research Institute for Automation and Measurements PIAP
Al. Jerozolimskie 202, 02-486 Warsaw, Poland
next prev parent reply other threads:[~2013-10-09 6:53 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-03 14:00 Suspected cache coherency problem on V4L2 and AR7100 CPU Krzysztof Hałasa
2013-10-04 8:06 ` Krzysztof Hałasa
2013-10-07 8:38 ` Krzysztof Hałasa
2013-10-07 14:24 ` Ralf Baechle
2013-10-08 8:24 ` Krzysztof Hałasa
2013-10-08 12:07 ` Ralf Baechle
2013-10-09 6:53 ` Krzysztof Hałasa [this message]
2013-10-09 8:17 ` Ralf Baechle
2013-10-09 13:05 ` Krzysztof Hałasa
2013-10-08 10:46 ` Krzysztof Hałasa
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