From: khalasa@piap.pl (Krzysztof Hałasa)
To: linux-mips@linux-mips.org
Cc: linux-media@vger.kernel.org
Subject: Re: Suspected cache coherency problem on V4L2 and AR7100 CPU
Date: Fri, 04 Oct 2013 10:06:45 +0200 [thread overview]
Message-ID: <m3a9ipa296.fsf@t19.piap.pl> (raw)
In-Reply-To: <m3eh82a1yo.fsf@t19.piap.pl> ("Krzysztof Hałasa"'s message of "Thu, 03 Oct 2013 16:00:47 +0200")
> I'm debugging a problem with a SOLO6110-based H.264 PCI video encoder on
> Atheros AR7100-based (MIPS, big-endian) platform.
BTW this CPU obviously has VIPT data cache, this means a physical page
with multiple virtual addresses (e.g. mapped multiple times) may and
will be cached multiple times.
AR7100 = arch/mips/ath79.
--
Krzysztof Halasa
Research Institute for Automation and Measurements PIAP
Al. Jerozolimskie 202, 02-486 Warsaw, Poland
next prev parent reply other threads:[~2013-10-04 8:06 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-03 14:00 Suspected cache coherency problem on V4L2 and AR7100 CPU Krzysztof Hałasa
2013-10-04 8:06 ` Krzysztof Hałasa [this message]
2013-10-07 8:38 ` Krzysztof Hałasa
2013-10-07 14:24 ` Ralf Baechle
2013-10-08 8:24 ` Krzysztof Hałasa
2013-10-08 12:07 ` Ralf Baechle
2013-10-09 6:53 ` Krzysztof Hałasa
2013-10-09 8:17 ` Ralf Baechle
2013-10-09 13:05 ` Krzysztof Hałasa
2013-10-08 10:46 ` Krzysztof Hałasa
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