Re: Sony IMX290/462 image sensors I2C xfer peculiarity

["Krzysztof Hałasa" <khalasa@piap.pl>]

Hi Dave,

thanks for your mail:

> What's your requirement to be able to read back so many registers at once?

Ah, I'm debugging I/O errors while trying to use the sensors, it was
only an example how to reliably trigger the problem.

> I currently can't see a reason for a sensor driver to be needing to do
> these big reads, so how can it cause a driver failure?

I2C doesn't specify a time limit for requests. Even doing basic things -
like enabling streaming - I sometimes get I/O errors ("arbitration
lost"). This is i.MX6MP platform using PIO-style hardware master I2C.
While the CPU has some DMA capability for I2C, it's apparently not used
in this case - maybe because the transfers are shorter than the
threshold.

BTW the "arbitration lost" means here a STOP was detected by the CPU.
This happens when the sensor stops pulling down SDA on timeout, in case
SCL was high at the time (SDA 0->1 with SCL high is technically STOP,
but there is only one master here - CPU - and only one I2C device - the
sensor, so it isn't a real STOP, it's just a sensor disconnection from
the I2C bus).

With 37.125 MHz master clock the time limit is ca. 7 ms - it's easy for
a short transfer to take more time, even on an otherwise idle system and
even with 400 kHz I2C clock.

It happens in init, while enabling streaming, while setting parameters
while streaming. Everytime a transfer crosses the magic ca. 7.06xx ms
time. No transfer can take more time than this value, I always get
a (false) STOP or the data being read becomes all ones.

> Scanning the IMX290 datasheet further, there is a slightly worrying
> paragraph in "Register Communication Timing (I2C)":
> "In I2C communication system, communication can be performed excluding
> during the period when communication is prohibited from the falling
> edge of XVS to 6H after (1H period)."
> and the diagram shows a 1 line period 6 lines after XVS which is
> marked "communication prohibited period". Ouch!

Right, I noticed this, but I don't think it's related. The issue can be
seen in idle as well.

> I've never experienced issues with I2C comms to these modules, but is
> it possible that you're hitting this period with your longer I2C
> transactions?

I'm just hitting a seemingly hard limit with long transfers (albeit it
may be quite short in terms of bytes - times between bytes are just long
due to scheduling and PIO-style byte-sized CPU access).

> A logic analyser looking at XVS, XHS, and the I2C might
> give you some clues.

TBH I didn't try to connect to XVS and XHS. My IMX290 modules don't even
have these signals (apparently -  there are "unused" connections).
I just observed that the timeout is 2^18 master cycles from the first
START. There it very little jitter here (on an oscilloscope - a fraction
of a microsecond). I haven't counted the exact master clock cycles #,
should I?

> Or are you not streaming when you're doing these
> transactions?

That's the case, too.

> IMX462 appears to list a similar restriction.
-- 
Krzysztof "Chris" Hałasa

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