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Thu, 08 Oct 2026 04:42:51 -0700 (PDT) X-Received: by 2002:a17:90b:5490:b0:3a6:d2ac:74ce with SMTP id 98e67ed59e1d1-3aaec84421fmr1220424a91.19.1791459771026; Thu, 08 Oct 2026 04:42:51 -0700 (PDT) Received: from [10.218.18.193] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3aa0cc1fbb2sm3776475a91.17.2026.10.08.04.42.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 08 Oct 2026 04:42:50 -0700 (PDT) Message-ID: <018b4233-8a2c-48b4-bbd6-4c471dd14568@oss.qualcomm.com> Date: Thu, 8 Oct 2026 17:12:43 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 05/14] ASoC: mediatek: mt8195: Fix paired memif clock error handling To: phucduc.bui@gmail.com, Mark Brown , AngeloGioacchino Del Regno , Trevor Wu Cc: Liam Girdwood , Matthias Brugger , Jaroslav Kysela , Takashi Iwai , Kuninori Morimoto , cassiogabrielcontato@gmail.com, Mukesh Ojha , Liviu Dudau , Haotian Zhang , HariKrishna Sagala , linux-sound@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, ajay.nandam@oss.qualcomm.com References: <20261005110257.50145-1-phucduc.bui@gmail.com> <20261005110257.50145-6-phucduc.bui@gmail.com> Content-Language: en-US From: Ajay Kumar Nandam In-Reply-To: <20261005110257.50145-6-phucduc.bui@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA4MDA0NiBTYWx0ZWRfXyl4zqwHdtj+E UPkrS/+G7BRe97ilRQYPVl1dK93pq74RkY3hlRhePJFeH3LQAsZP1Dt+oVkApZtCefiKU5tI6+L 0SXcMmAa1ioAO5d7Bb9pD953tJBQoUI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA4MDA0NiBTYWx0ZWRfX+09bkW7/DEK1 YWKyPNJyxeLtlSAz3nwhgpDQ1L000gG363zvtF8fKlXVYoD1B1puv6wqnFQ84PJuGGHm4zJSG2X /RsiwEcjNaR12uC/U9iyErI+zkKOUGYKhiVXsLjdeEKy+gZTqx1JGOe1P84fFJ2SJ7QCS8DVSfo e0EZx5a+vX2z9pb4/ajqc+y2w4BYOlUGHwFB2sMzZd44RYO287FOWE4RPzzXoWEnsx0SJqrNbqi V9pWXOhJ9G4DEavc6UyU+WPCQr4ICfmVpd/d1QH9DrFC6XsyMupTdb0Orm2Zi1bpI9TduOJK0Gt uGc3+GHMpErDWmZTa/i+6YC0dvZMtf6/o0uP+LFj3dWcwh4lQOq4DyT+Uxpt3LjWvsFK9S1g7Lb JaG38vsi5e/a+8WO4PtsGL+/XLKM0I/zidujQjs1yipNO5teonjSh2JOBQMGJEvZGYZQqe1scOM 4GmkRpmbh3ac76sW2EQ== X-Proofpoint-ORIG-GUID: ki96Cark0oYk1wyT3jHq5985O7RAwWd5 X-Proofpoint-GUID: ki96Cark0oYk1wyT3jHq5985O7RAwWd5 X-Authority-Analysis: v=2.4 cv=CIm/zhrD c=1 sm=1 tr=0 ts=6ac781bc cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=pGLkceISAAAA:8 a=JvgeKo86Odfbx7RWJVYA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-08_04,2026-10-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 adultscore=0 spamscore=0 priorityscore=1501 suspectscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610020000 definitions=main-2610080046 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261008_044252_937666_B9B5A3D7 X-CRM114-Status: GOOD ( 21.38 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On 10/5/2026 4:32 PM, phucduc.bui@gmail.com wrote: > From: bui duc phuc > > Check and propagate errors when preparing and enabling the paired > DL8/DL10 memif clocks. > > If enabling the second clock fails, undo the clock that was already > prepared or enabled to keep the clock state balanced. > > Fixes: 6746cc858259 ("ASoC: mediatek: mt8195: add platform driver") > Signed-off-by: bui duc phuc > --- > sound/soc/mediatek/mt8195/mt8195-afe-pcm.c | 24 ++++++++++++++++++---- > 1 file changed, 20 insertions(+), 4 deletions(-) > > diff --git a/sound/soc/mediatek/mt8195/mt8195-afe-pcm.c b/sound/soc/mediatek/mt8195/mt8195-afe-pcm.c > index 52c3381e6766..1d3e01e2c3e7 100644 > --- a/sound/soc/mediatek/mt8195/mt8195-afe-pcm.c > +++ b/sound/soc/mediatek/mt8195/mt8195-afe-pcm.c > @@ -286,15 +286,23 @@ mt8195_afe_paired_memif_clk_prepare(struct snd_pcm_substream *substream, > struct mt8195_afe_private *afe_priv = afe->platform_priv; > int id = snd_soc_rtd_to_cpu(rtd, 0)->id; > int clk_id; > + int ret; > > if (id != MT8195_AFE_MEMIF_DL8 && id != MT8195_AFE_MEMIF_DL10) > return 0; > > if (enable) { > clk_id = MT8195_CLK_AUD_MEMIF_DL10; > - mt8195_afe_prepare_clk(afe, afe_priv->clk[clk_id]); > + ret = mt8195_afe_prepare_clk(afe, afe_priv->clk[clk_id]); > + if (ret) > + return ret; > clk_id = MT8195_CLK_AUD_MEMIF_DL8; > - mt8195_afe_prepare_clk(afe, afe_priv->clk[clk_id]); > + ret = mt8195_afe_prepare_clk(afe, afe_priv->clk[clk_id]); > + if (ret) { > + clk_id = MT8195_CLK_AUD_MEMIF_DL10; > + mt8195_afe_unprepare_clk(afe, afe_priv->clk[clk_id]); > + return ret; > + } > } else { > clk_id = MT8195_CLK_AUD_MEMIF_DL8; > mt8195_afe_unprepare_clk(afe, afe_priv->clk[clk_id]); > @@ -315,6 +323,7 @@ mt8195_afe_paired_memif_clk_enable(struct snd_pcm_substream *substream, > struct mt8195_afe_private *afe_priv = afe->platform_priv; > int id = snd_soc_rtd_to_cpu(rtd, 0)->id; > int clk_id; > + int ret; > > if (id != MT8195_AFE_MEMIF_DL8 && id != MT8195_AFE_MEMIF_DL10) > return 0; > @@ -322,11 +331,18 @@ mt8195_afe_paired_memif_clk_enable(struct snd_pcm_substream *substream, > if (enable) { > /* DL8_DL10_MEM */ > clk_id = MT8195_CLK_AUD_MEMIF_DL10; > - mt8195_afe_enable_clk_atomic(afe, afe_priv->clk[clk_id]); > + ret = mt8195_afe_enable_clk_atomic(afe, afe_priv->clk[clk_id]); > + if (ret) > + return ret; > udelay(1); > /* DL8_DL10_AGENT */ > clk_id = MT8195_CLK_AUD_MEMIF_DL8; > - mt8195_afe_enable_clk_atomic(afe, afe_priv->clk[clk_id]); > + ret = mt8195_afe_enable_clk_atomic(afe, afe_priv->clk[clk_id]); > + if (ret) { > + clk_id = MT8195_CLK_AUD_MEMIF_DL10; > + mt8195_afe_disable_clk_atomic(afe, afe_priv->clk[clk_id]); > + return ret; > + } This makes mt8195_afe_paired_memif_clk_enable() return failures from the paired DL8/DL10 clock enables, but the return value still appears to be dropped by the trigger path. After applying the full series, mt8195_afe_fe_trigger() still calls the enable helper like this on START/RESUME: mt8195_afe_paired_memif_clk_enable(substream, dai, 1); so a failure from clk_enable() would not be propagated back through the DAI .trigger callback. Patch 6 handles the prepare-side helper in startup(), but I do not see the enable-side helper being handled by any later patch. Should the START/RESUME path check this return value and unwind the trigger state if enabling the paired MEMIF clock fails? Thanks Ajay Kumar Nandam > } else { > /* DL8_DL10_AGENT */ > clk_id = MT8195_CLK_AUD_MEMIF_DL8;