Re: [PATCH] PCI: Mark Nvidia GB10 to avoid bus reset

[Terje Bergstrom <tbergstrom@nvidia.com>]

On 1/15/26 12:53, Bjorn Helgaas wrote:
> OK, so you do SBR to some endpoint below a GB10 Root Port, and after > the SBR, the link to the endpoint retrains with a lower lane count > and config reads to the endpoint time out?

That's right. The symptoms can vary, i.e. sometimes it retrains with lower
lane count, and sometimes config reads start timing out, and very often
it works just fine.

> I see you're from NVIDIA, so if you're confirming that this is a > hardware erratum (not an issue with the GB10 PCI controller driver), > we should definitely apply this, and I'll wordsmith the commit log > and comment something like this: > > When asserting Secondary Bus Reset to downstream devices via a GB10 > Root Port, the link doesn't retrain correctly. The link may retrain > with a lower lane count, and config accesses to downstream devices > may fail.

Yes, I confirm this is a HW erratum. The problem doesn't occur every time, so
"the link may not retrain correctly" would be more correct, but that's a minor
comment.

Terje