From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88BDBC433FE for ; Tue, 15 Nov 2022 09:25:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=xj/LOI+SOXgI2F6EhVRW7eCDcJfOBqSLw+ng7G843AU=; b=mokK8Kg6gI0mdzrLXD8tmcEZkK xQinKP06PqHxg+SMaUu/zj7//qhpgl67ckziKdteh9tycdZMZJaBwzW1gYWwybGfqZAu+qmbPazlj THXNjjrXz0OOCkDC0RHso5/vOjTmVYzCEieffNShohCfdl7v3KgE+84FbdQhFrjA+2s4d5ZKdjZrl d27qYFl0WI2uYqamWycFwVH8TuAsua8+BgvtGBIIqx9G9k7qDb3ADu5yGclsQ0p2Ynxt3ZejwI4/I B8QjhOqrrpJcj2OGrQRwmmo5Kh8q+FadZ42Nrv14qJs5gcv3yaNl8N0NzSSbCMEfgUblcareK1RwI Jehh+Bmg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ousCP-009MFd-54; Tue, 15 Nov 2022 09:25:45 +0000 Received: from madras.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e5ab]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ousAU-009Kjt-A1; Tue, 15 Nov 2022 09:23:49 +0000 Received: from [192.168.1.100] (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 2506B6602A0B; Tue, 15 Nov 2022 09:23:44 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668504224; bh=14FQ7XdqqsKx0ej8JuWfiLjDWW2DPMX5zWGMoAJNGTA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=k/cEielxKpv0q0nEXJ/AjD/MsoeMhII1oHBnMxtgdg5aVJk0Y9YA5vhrJdOVdj3CY LNtFL9+F1gi3tbf1HZz3+x8iTWeJjJksuzpbNCxfdQGijOlj+LsBOuP/PxYnMOdppi zfP5+9Loe+kO9Z0l1PdBFPTgYdgbfj5vVMEZu8cYQ6rI1c6jgGOSOG9wjJMtP4e1ay nzCI0u8Dk3P16KU7aqMgGJn+WGcA+vesDNaShqwR/1QoyqLK7Duv3EYwmjU58QlEEA DVdhR3GK4G2bX/dmt19lYJMKm6fioBg8QlnCzGBLcZefP7ysBfjTcuWL52t4s3i5Pu /bmYXqOotSTxw== Message-ID: <13f01920-5a7c-65a4-7907-7116e365f18e@collabora.com> Date: Tue, 15 Nov 2022 10:23:41 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.3 Subject: Re: [PATCH v2 01/15] arm64: dts: mediatek: Initial mt8365-evk support Content-Language: en-US To: =?UTF-8?Q?Bernhard_Rosenkr=c3=a4nzer?= , linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com References: <20221107211001.257393-1-bero@baylibre.com> <20221115025421.59847-1-bero@baylibre.com> <20221115025421.59847-2-bero@baylibre.com> From: AngeloGioacchino Del Regno In-Reply-To: <20221115025421.59847-2-bero@baylibre.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221115_012346_679663_3A36E4F5 X-CRM114-Status: GOOD ( 20.99 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Il 15/11/22 03:54, Bernhard Rosenkränzer ha scritto: > From: Fabien Parent > > This adds minimal support for the Mediatek 8365 SOC and the EVK reference > board, allowing the board to boot to initramfs with serial port I/O. > > GPIO keys are supported, MMC is partially supported (needs the clocks > driver for full support). > > Signed-off-by: Fabien Parent > [bero@baylibre.com: Removed parts depending on drivers that aren't upstream yet, cleanups] > Signed-off-by: Bernhard Rosenkränzer > --- > arch/arm64/boot/dts/mediatek/Makefile | 1 + > arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 344 +++++++++++ > arch/arm64/boot/dts/mediatek/mt8365.dtsi | 601 ++++++++++++++++++++ > 3 files changed, 946 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > index 0ec90cb3ef289..e668fd50a3326 100644 > --- a/arch/arm64/boot/dts/mediatek/Makefile > +++ b/arch/arm64/boot/dts/mediatek/Makefile > @@ -46,4 +46,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb > diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts > new file mode 100644 > index 0000000000000..74e0f75231637 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts > @@ -0,0 +1,344 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2021-2022 BayLibre, SAS. > + * Authors: > + * Fabien Parent > + * Bernhard Rosenkränzer > + */ > + > +/dts-v1/; > + > +#include > +#include > +#include > +#include "mt8365.dtsi" > + > +/ { > + model = "MediaTek MT8365 Open Platform EVK"; > + compatible = "mediatek,mt8365-evk", "mediatek,mt8365"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:921600n8"; > + }; > + > + firmware { > + optee { > + compatible = "linaro,optee-tz"; > + method = "smc"; > + }; > + }; > + > + gpio-keys { > + compatible = "gpio-keys"; > + input-name = "gpio-keys"; > + pinctrl-names = "default"; > + pinctrl-0 = <&gpio_keys>; > + > + key-volume-up { > + gpios = <&pio 24 GPIO_ACTIVE_LOW>; > + label = "volume_up"; > + linux,code = ; > + wakeup-source; > + debounce-interval = <15>; > + }; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0 0x40000000 0 0xc0000000>; > + }; > + > + usb_otg_vbus: regulator-0 { > + compatible = "regulator-fixed"; > + regulator-name = "otg_vbus"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&pio 16 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + /* 12 MiB reserved for OP-TEE (BL32) > + * +-----------------------+ 0x43e0_0000 > + * | SHMEM 2MiB | > + * +-----------------------+ 0x43c0_0000 > + * | | TA_RAM 8MiB | > + * + TZDRAM +--------------+ 0x4340_0000 > + * | | TEE_RAM 2MiB | > + * +-----------------------+ 0x4320_0000 > + */ > + optee_reserved: optee@43200000 { > + no-map; > + reg = <0 0x43200000 0 0x00c00000>; > + }; > + }; > +}; > + > +&i2c1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&i2c1_pins>; > + clock-frequency = <100000>; > + status = "okay"; > +}; > + > +&pio { > + dpi_func_pins: dpi-func-pins { > + pins { > + pinmux = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + drive-strength = ; > + }; > + }; > + > + dpi_idle_pins: dpi-idle-pins { > + pins { > + pinmux = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + }; > + }; > + > + gpio_keys: gpio-keys-pins { > + pins { > + pinmux = ; > + bias-pull-up; > + input-enable; > + }; > + }; > + > + i2c1_pins: i2c1-pins { > + pins { > + pinmux = , > + ; > + mediatek,pull-up-adv = <3>; > + mediatek,drive-strength-adv = <00>; > + bias-pull-up; > + }; > + }; > + > + ite_pins: ite-pins { > + pins-rst-ite { > + pinmux = ; > + output-high; > + }; > + > + pins-irq-ite { > + pinmux = ; > + input-enable; > + bias-pull-up; > + }; > + > + pins-pwr { > + pinmux = , > + ; > + output-high; > + }; > + }; > + > + mmc0_pins_default: mmc0-default-pins { > + pins-clk { > + pinmux = ; > + bias-pull-down; > + }; > + > + pins-cmd-dat { > + pinmux = , > + , > + , > + , > + , > + , > + , > + , > + ; > + input-enable; > + bias-pull-up; > + }; > + > + pins-rst { > + pinmux = ; > + bias-pull-up; > + }; > + }; > + > + mmc0_pins_uhs: mmc0-uhs-pins { > + pins-clk { > + pinmux = ; > + drive-strength = ; > + bias-pull-down = ; > + }; > + > + pins-cmd-dat { > + pinmux = , > + , > + , > + , > + , > + , > + , > + , > + ; > + input-enable; > + drive-strength = ; > + bias-pull-up = ; > + }; > + > + pins-ds { > + pinmux = ; > + drive-strength = ; > + bias-pull-down = ; > + }; > + > + pins-rst { > + pinmux = ; > + drive-strength = ; > + bias-pull-up; > + }; > + }; > + > + mmc1_pins_default: mmc1-default-pins { > + pins-cd { > + pinmux = ; > + bias-pull-up; > + }; > + > + pins-clk { > + pinmux = ; > + bias-pull-down = ; > + }; > + > + pins-cmd-dat { > + pinmux = , > + , > + , > + , > + ; > + input-enable; > + bias-pull-up = ; > + }; > + }; > + > + mmc1_pins_uhs: mmc1-uhs-pins { > + pins-clk { > + pinmux = ; > + drive-strength = ; > + bias-pull-down = ; > + }; > + > + pins-cmd-dat { > + pinmux = , > + , > + , > + , > + ; > + input-enable; > + drive-strength = ; > + bias-pull-up = ; > + }; > + }; > + > + uart0_pins: uart0-pins { > + pins { > + pinmux = , > + ; > + }; > + }; > + > + uart1_pins: uart1-pins { > + pins { > + pinmux = , > + ; > + }; > + }; > + > + uart2_pins: uart2-pins { > + pins { > + pinmux = , > + ; > + }; > + }; > + > + usb_pins: usb-pins { > + pins-id { > + pinmux = ; > + input-enable; > + bias-pull-up; > + }; > + > + pins-usb0-vbus { > + pinmux = ; > + output-high; > + }; > + > + pin-usb1-vbus { > + pinmux = ; > + output-high; > + }; > + }; > + > + pwm_pins: pwm-pins { > + pins { > + pinmux = , > + ; > + }; > + }; > +}; > + > +&pwm { > + pinctrl-0 = <&pwm_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&uart0 { > + pinctrl-0 = <&uart0_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&uart1 { > + pinctrl-0 = <&uart1_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&uart2 { > + pinctrl-0 = <&uart2_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi > new file mode 100644 > index 0000000000000..1cf2172081b20 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi > @@ -0,0 +1,601 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * (C) 2018 MediaTek Inc. > + * Copyright (C) 2022 BayLibre SAS > + * Fabien Parent > + * Bernhard Rosenkränzer > + */ > +#include > +#include > +#include > +#include > +#include > + > +/ { > + compatible = "mediatek,mt8365"; > + interrupt-parent = <&sysirq>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus: cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0: cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x0>; > + #cooling-cells = <2>; I don't see any CPU caches and I'm totally sure that this SoC does have a unified 512KB unified L2 cache. > + enable-method = "psci"; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x1>; > + #cooling-cells = <2>; > + enable-method = "psci"; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x2>; > + #cooling-cells = <2>; > + enable-method = "psci"; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x3>; > + #cooling-cells = <2>; > + enable-method = "psci"; > + }; > + }; > + > + clk26m: oscillator { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <26000000>; > + clock-output-names = "clk26m"; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; Does this SoC really not support any idle-state?! Seems pretty odd. > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ > + bl31_secmon_reserved: secmon@43000000 { > + no-map; > + reg = <0 0x43000000 0 0x20000>; > + }; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + ranges; > + > + gic: interrupt-controller@c000000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <4>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + reg = <0 0x0c000000 0 0x80000>, > + <0 0x0c080000 0 0x80000>; > + > + interrupts = ; > + }; > + > + topckgen: syscon@10000000 { > + compatible = "mediatek,mt8365-topckgen", "syscon"; > + reg = <0 0x10000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + infracfg: syscon@10001000 { > + compatible = "mediatek,mt8365-infracfg", "syscon"; > + reg = <0 0x10001000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + pericfg: syscon@10003000 { > + compatible = "mediatek,mt8365-pericfg", "syscon"; > + reg = <0 0x10003000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + syscfg_pctl: syscfg-pctl@10005000 { > + compatible = "mediatek,mt8365-syscfg", "syscon"; > + reg = <0 0x10005000 0 0x1000>; > + }; > + > + watchdog: watchdog@10007000 { > + compatible = "mediatek,mt8365-wdt", > + "mediatek,mt6589-wdt"; 83 cols is fine, fits in one line. > + reg = <0 0x10007000 0 0x100>; > + #reset-cells = <1>; > + }; > + > + gpt: apxgpt@10008000 { This should be timer@10008000 > + compatible = "mediatek,mt8365-timer", > + "mediatek,mt6577-timer"; > + reg = <0 0x10008000 0 0x1000>; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_SYS_26M_D2>; > + clock-names = "clk13m"; > + }; > + ..snip.. > + > + infracfg: infracfg@1020e000 { > + compatible = "mediatek,mt8365-infracfg", "syscon"; > + reg = <0 0x1020e000 0 0x1000>; > + }; > + > + rng: rng@1020f000 { > + compatible = "mediatek,mt8365-rng", > + "mediatek,mt7623-rng"; Fits in one line. > + reg = <0 0x1020f000 0 0x100>; > + clocks = <&infracfg CLK_IFR_TRNG>; > + clock-names = "rng"; > + }; > + ..snip.. > + > + uart0: serial@11002000 { > + compatible = "mediatek,mt8365-uart", > + "mediatek,mt6577-uart"; 85 cols is probably fine, so this should fit in one line. > + reg = <0 0x11002000 0 0x1000>; > + interrupts = ; > + clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; > + clock-names = "baud", "bus"; > + dmas = <&apdma 0>, <&apdma 1>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + ..snip.. > + > + i2c0: i2c@11007000 { > + compatible = "mediatek,mt8365-i2c", > + "mediatek,mt8168-i2c"; Fits in one line. > + reg = <0 0x11007000 0 0xa0>, > + <0 0x11000080 0 0x80>; Same. > + interrupts = ; > + clock-div = <1>; > + clocks = <&infracfg CLK_IFR_I2C0_AXI>, > + <&infracfg CLK_IFR_AP_DMA>; > + clock-names = "main", "dma"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c1: i2c@11008000 { > + compatible = "mediatek,mt8365-i2c", > + "mediatek,mt8168-i2c"; > + reg = <0 0x11008000 0 0xa0>, > + <0 0x11000100 0 0x80>; ...again... > + interrupts = ; > + clock-div = <1>; > + clocks = <&infracfg CLK_IFR_I2C1_AXI>, > + <&infracfg CLK_IFR_AP_DMA>; > + clock-names = "main", "dma"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c2: i2c@11009000 { > + compatible = "mediatek,mt8365-i2c", > + "mediatek,mt8168-i2c"; > + reg = <0 0x11009000 0 0xa0>, > + <0 0x11000180 0 0x80>; ...and again... > + interrupts = ; > + clock-div = <1>; > + clocks = <&infracfg CLK_IFR_I2C2_AXI>, > + <&infracfg CLK_IFR_AP_DMA>; > + clock-names = "main", "dma"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi: spi@1100a000 { > + compatible = "mediatek,mt8365-spi", > + "mediatek,mt7622-spi"; ...and it's the same here again... I'll stop saying the same at every instance, so please check the others :-) > + reg = <0 0x1100a000 0 0x100>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, > + <&topckgen CLK_TOP_SPI_SEL>, > + <&infracfg CLK_IFR_SPI0>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + status = "disabled"; > + }; > + Regards, Angelo