Linux-mediatek Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Bibby Hsieh <bibby.hsieh@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>
Cc: David Airlie <airlied@linux.ie>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Daniel Vetter <daniel.vetter@ffwll.ch>,
	dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	Yingjoe Chen <yingjoe.chen@mediatek.com>,
	Cawa Cheng <cawa.cheng@mediatek.com>,
	Daniel Kurtz <djkurtz@chromium.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	YT Shen <yt.shen@mediatek.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	Mao Huang <littlecvr@chromium.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Sascha Hauer <kernel@pengutronix.de>,
	Junzhi Zhao <junzhi.zhao@mediatek.com>
Subject: Re: [PATCH 2/4] drm/mediatek: enhance the HDMI driving current
Date: Mon, 25 Jul 2016 14:15:35 +0800	[thread overview]
Message-ID: <1469427335.26205.12.camel@mtksdaap41> (raw)
In-Reply-To: <1468998902.11841.54.camel@mtksdaap41>

Hi, CK,

I'm appreciate your comment.

On Wed, 2016-07-20 at 15:15 +0800, CK Hu wrote:
> Hi, Bibby:
> 
> One comment inline.
> 
> On Wed, 2016-07-20 at 12:03 +0800, Bibby Hsieh wrote:
> > From: Junzhi Zhao <junzhi.zhao@mediatek.com>
> > 
> > In order to improve 4K resolution performance,
> > we have to enhance the HDMI driving currend
> > when clock rate is greater than 165MHz.
> > 
> > Signed-off-by: Junzhi Zhao <junzhi.zhao@mediatek.com>
> > Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c |   89 +++++++++++++++++-------
> >  1 file changed, 63 insertions(+), 26 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> > index 8a24754..a871c14 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> > @@ -298,32 +298,69 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> >  			  (0x1 << PLL_BR_SHIFT),
> >  			  RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
> >  			  RG_HDMITX_PLL_BR);
> > -	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
> > -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
> > -			  (0x3 << PRD_IBIAS_CLK_SHIFT) |
> > -			  (0x3 << PRD_IBIAS_D2_SHIFT) |
> > -			  (0x3 << PRD_IBIAS_D1_SHIFT) |
> > -			  (0x3 << PRD_IBIAS_D0_SHIFT),
> > -			  RG_HDMITX_PRD_IBIAS_CLK |
> > -			  RG_HDMITX_PRD_IBIAS_D2 |
> > -			  RG_HDMITX_PRD_IBIAS_D1 |
> > -			  RG_HDMITX_PRD_IBIAS_D0);
> > -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
> > -			  (0x0 << DRV_IMP_EN_SHIFT), RG_HDMITX_DRV_IMP_EN);
> > -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
> > -			  (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
> > -			  (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
> > -			  (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
> > -			  (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
> > -			  RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
> > -			  RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
> > -	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
> > -			  (hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) |
> > -			  (hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) |
> > -			  (hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) |
> > -			  (hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT),
> > -			  RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 |
> > -			  RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0);
> > +	if (rate < 165000000) {
> > +		mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
> > +					RG_HDMITX_PRD_IMP_EN);
> > +		mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
> > +				  (0x3 << PRD_IBIAS_CLK_SHIFT) |
> > +				  (0x3 << PRD_IBIAS_D2_SHIFT) |
> > +				  (0x3 << PRD_IBIAS_D1_SHIFT) |
> > +				  (0x3 << PRD_IBIAS_D0_SHIFT),
> > +				  RG_HDMITX_PRD_IBIAS_CLK |
> > +				  RG_HDMITX_PRD_IBIAS_D2 |
> > +				  RG_HDMITX_PRD_IBIAS_D1 |
> > +				  RG_HDMITX_PRD_IBIAS_D0);
> > +		mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
> > +				  (0x0 << DRV_IMP_EN_SHIFT),
> > +				  RG_HDMITX_DRV_IMP_EN);
> > +		mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
> > +				  (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
> > +				  (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
> > +				  (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
> > +				  (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
> > +				  RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
> > +				  RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
> > +		mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
> > +				  (hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) |
> > +				  (hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) |
> > +				  (hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) |
> > +				  (hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT),
> > +				  RG_HDMITX_DRV_IBIAS_CLK |
> > +				  RG_HDMITX_DRV_IBIAS_D2 |
> > +				  RG_HDMITX_DRV_IBIAS_D1 |
> > +				  RG_HDMITX_DRV_IBIAS_D0);
> > +	} else {
> > +		mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
> > +				      RG_HDMITX_PRD_IMP_EN);
> > +		mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
> > +				  (0x6 << PRD_IBIAS_CLK_SHIFT) |
> > +				  (0x6 << PRD_IBIAS_D2_SHIFT) |
> > +				  (0x6 << PRD_IBIAS_D1_SHIFT) |
> > +				  (0x6 << PRD_IBIAS_D0_SHIFT),
> > +				  RG_HDMITX_PRD_IBIAS_CLK |
> > +				  RG_HDMITX_PRD_IBIAS_D2 |
> > +				  RG_HDMITX_PRD_IBIAS_D1 |
> > +				  RG_HDMITX_PRD_IBIAS_D0);
> > +		mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
> > +				  (0xf << DRV_IMP_EN_SHIFT),
> > +				  RG_HDMITX_DRV_IMP_EN);
> > +		mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
> > +				  (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
> > +				  (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
> > +				  (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
> > +				  (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
> > +				  RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
> > +				  RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
> > +		mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
> > +				  (hdmi_phy->ibias_up << DRV_IBIAS_CLK_SHIFT) |
> > +				  (hdmi_phy->ibias_up << DRV_IBIAS_D2_SHIFT) |
> > +				  (hdmi_phy->ibias_up << DRV_IBIAS_D1_SHIFT) |
> > +				  (hdmi_phy->ibias_up << DRV_IBIAS_D0_SHIFT),
> > +				  RG_HDMITX_DRV_IBIAS_CLK |
> > +				  RG_HDMITX_DRV_IBIAS_D2 |
> > +				  RG_HDMITX_DRV_IBIAS_D1 |
> > +				  RG_HDMITX_DRV_IBIAS_D0);
> > +	}
> 
> 'if' part and 'else' part looks almost the same. Use variable for
> difference and merge these two part. For example:
> 
> if (rate < 165000000)
> 	prd_ibias = 0x3;
> else
> 	prd_ibias = 0x6;
> 
> mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
> 		  (prd_ibias << PRD_IBIAS_CLK_SHIFT) |
> 		  (prd_ibias << PRD_IBIAS_D2_SHIFT) |
> 		  (prd_ibias << PRD_IBIAS_D1_SHIFT) |
> 		  (prd_ibias << PRD_IBIAS_D0_SHIFT),
> 		  RG_HDMITX_PRD_IBIAS_CLK |
> 		  RG_HDMITX_PRD_IBIAS_D2 |
> 		  RG_HDMITX_PRD_IBIAS_D1 |
> 		  RG_HDMITX_PRD_IBIAS_D0);
> 
> >  	return 0;
> >  }
> >  
Ok, I will use variable instead of that.
> 
> Regards,
> CK
> 

  reply	other threads:[~2016-07-25  6:15 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-20  4:03 [PATCH 0/4] MT8173 HDMI 4K support Bibby Hsieh
2016-07-20  4:03 ` [PATCH 1/4] drm/mediatek: do mtk_hdmi_send_infoframe after HDMI clock enable Bibby Hsieh
     [not found] ` <1468987385-37353-1-git-send-email-bibby.hsieh-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2016-07-20  4:03   ` [PATCH 2/4] drm/mediatek: enhance the HDMI driving current Bibby Hsieh
2016-07-20  7:15     ` CK Hu
2016-07-25  6:15       ` Bibby Hsieh [this message]
2016-07-20  4:03 ` [PATCH 3/4] drm/mediatek: fix the wrong pixel clock when resolution is 4K Bibby Hsieh
2016-07-20  7:57   ` CK Hu
2016-07-25  6:24     ` Bibby Hsieh
2016-07-25  6:49       ` CK Hu
2016-07-25  8:37         ` Bibby Hsieh
2016-07-20  9:41   ` Philipp Zabel
2016-07-25  6:25     ` Bibby Hsieh
2016-07-20  4:03 ` [PATCH 4/4] drm/mediatek: adjust VENCPLL clock for 4K HDMI output Bibby Hsieh
2016-07-20  9:55   ` Philipp Zabel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1469427335.26205.12.camel@mtksdaap41 \
    --to=bibby.hsieh@mediatek.com \
    --cc=airlied@linux.ie \
    --cc=cawa.cheng@mediatek.com \
    --cc=ck.hu@mediatek.com \
    --cc=daniel.vetter@ffwll.ch \
    --cc=djkurtz@chromium.org \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=junzhi.zhao@mediatek.com \
    --cc=kernel@pengutronix.de \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mediatek@lists.infradead.org \
    --cc=littlecvr@chromium.org \
    --cc=matthias.bgg@gmail.com \
    --cc=p.zabel@pengutronix.de \
    --cc=thierry.reding@gmail.com \
    --cc=yingjoe.chen@mediatek.com \
    --cc=yt.shen@mediatek.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox