From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rick Chang Subject: [PATCH v4 1/3] dt-bindings: mediatek: Add a binding for Mediatek JPEG Decoder Date: Mon, 7 Nov 2016 14:57:17 +0800 Message-ID: <1478501839-2775-2-git-send-email-rick.chang@mediatek.com> References: <1478501839-2775-1-git-send-email-rick.chang@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1478501839-2775-1-git-send-email-rick.chang@mediatek.com> Sender: linux-kernel-owner@vger.kernel.org To: Hans Verkuil , Laurent Pinchart , Mauro Carvalho Chehab , Matthias Brugger Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, srv_heupstream@mediatek.com, linux-mediatek@lists.infradead.org, Minghsiu Tsai , Rick Chang List-Id: linux-mediatek@lists.infradead.org Add a DT binding documentation for Mediatek JPEG Decoder of MT2701 SoC. Signed-off-by: Rick Chang Signed-off-by: Minghsiu Tsai --- .../bindings/media/mediatek-jpeg-codec.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek-jpeg-codec.txt diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-codec.txt b/Documentation/devicetree/bindings/media/mediatek-jpeg-codec.txt new file mode 100644 index 0000000..c7dbcc2 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-codec.txt @@ -0,0 +1,35 @@ +* Mediatek JPEG Decoder + +Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs + +Required properties: +- compatible : "mediatek,jpgdec" +- reg : physical base address of the jpeg decoder registers and length of + memory mapped region. +- interrupts : interrupt number to the interrupt controller. +- clocks: device clocks, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- clock-names: must contain "jpgdec-smi" and "jpgdec". +- power-domains: a phandle to the power domain, see + Documentation/devicetree/bindings/power/power_domain.txt for details. +- mediatek,larb: must contain the local arbiters in the current Socs, see + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt + for details. +- iommus: should point to the respective IOMMU block with master port as + argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt + for details. + +Example: + jpegdec: jpegdec@15004000 { + compatible = "mediatek,jpgdec"; + reg = <0 0x15004000 0 0x1000>; + interrupts = ; + clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, + <&imgsys CLK_IMG_JPGDEC>; + clock-names = "jpgdec-smi", + "jpgdec"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + mediatek,larb = <&larb2>; + iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, + <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; + }; -- 1.9.1