Re: [SPAM]Re: [PATCH] PCI: Mediatek: Use resource_size function on resource object

Honghui Zhang
2019-01-31T02:26:25Z

On Wed, 2019-01-30 at 10:03 -0600, Bjorn Helgaas wrote:
> On Wed, Jan 02, 2019 at 02:03:53PM +0800, honghui.zhang@mediatek.com wrote:
> > From: Honghui Zhang <honghui.zhang@mediatek.com>
> >
> > drivers/pci/pcie-mediatek.c:720:13-16: WARNING: Suspicious code. resource_size is maybe missing with mem
> >
> > Generated by: scripts/coccinelle/api/resource_size.cocci
> >
> > Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> > ---
> > drivers/pci/controller/pcie-mediatek.c | 4 +---
> > 1 file changed, 1 insertion(+), 3 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> > index e307166..0168376 100644
> > --- a/drivers/pci/controller/pcie-mediatek.c
> > +++ b/drivers/pci/controller/pcie-mediatek.c
> > @@ -654,7 +654,6 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
> > struct resource *mem = &pcie->mem;
> > const struct mtk_pcie_soc *soc = port->pcie->soc;
> > u32 val;
> > - size_t size;
> > int err;
> >
> > /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
> > @@ -706,8 +705,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
> > mtk_pcie_enable_msi(port);
> >
> > /* Set AHB to PCIe translation windows */
> > - size = mem->end - mem->start;
> > - val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
> > + val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(resource_size(mem)));
> > writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
> >
> > val = upper_32_bits(mem->start);
>
> Unrelated to this patch, but just below this:
>
> /* Set PCIe to AXI translation memory space.*/
> val = fls(0xffffffff) | WIN_ENABLE;
> writel(val, port->base + PCIE_AXI_WINDOW0);
>
> Can you double-check the use of "fls(0xffffffff)"? That expression is
> a constant and I think evaluates to 31 (0x1f), i.e.,
>
> val = 0x1f | WIN_ENABLE;
>
> I don't know the hardware, so this might be correct, but
> "fls(0xffffffff)" looks funny because I think it's the same as
> "fls(0x80000000)".
>
HW design point it out that the window size is 2^x, the original code
set x as fls(0xffffffff), which is equal to 31.

The HW design possible values for PCIE_AXI_WINDOW0 size would be 12 to
36, which means that the PCIE2AXI will translate the 2^12 ~ 2^36 window
size. Which means that EP could access memory address from 0 to
2^12~2^36.

Since most of our HW(like MT2712 and MT7622) are all have 4GB DRAM size,
the proper size values should be 32 to enable EP DMA access all the DRAM
in RC. But since all the DRAM start from 0x4000_0000, So the value for
the size should be 33 to fit all the EP DMA memory access request.

I will send another patch to fix this.

Thanks for your kindly review.

> Bjorn