From: CK Hu <ck.hu@mediatek.com>
To: Jitao Shi <jitao.shi@mediatek.com>
Cc: srv_heupstream@mediatek.com, David Airlie <airlied@linux.ie>,
stonea168@163.com, cawa.cheng@mediatek.com,
dri-devel@lists.freedesktop.org, sj.huang@mediatek.com,
linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
yingjoe.chen@mediatek.com, eddie.huang@mediatek.com
Subject: Re: [PATCH v7 1/5] dt-bindings: display: mediatek: update dsi supported chips
Date: Mon, 23 Sep 2019 13:36:21 +0800 [thread overview]
Message-ID: <1569216981.20872.3.camel@mtksdaap41> (raw)
In-Reply-To: <20190920090432.3308-2-jitao.shi@mediatek.com>
Hi, Jitao:
On Fri, 2019-09-20 at 17:04 +0800, Jitao Shi wrote:
> Update device tree binding documentation for the dsi for
> Mediatek MT8183 SoCs.
>
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> Acked-by: Rob Herring <robh@kernel.org>
This version is different with previous version [1], so I think you
should drop the 'Acked-by' tag.
[1] https://patchwork.kernel.org/patch/11081701/
Regards,
CK
> ---
> .../bindings/display/mediatek/mediatek,dsi.txt | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> index fadf327c7cdf..993ff079ac09 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> @@ -7,7 +7,7 @@ channel output.
>
> Required properties:
> - compatible: "mediatek,<chip>-dsi"
> - the supported chips are mt2701 and mt8173.
> + the supported chips are mt2701, mt8173 and mt8183.
> - reg: Physical base address and length of the controller's registers
> - interrupts: The interrupt signal from the function block.
> - clocks: device clocks
> @@ -26,22 +26,31 @@ The MIPI TX configuration module controls the MIPI D-PHY.
>
> Required properties:
> - compatible: "mediatek,<chip>-mipi-tx"
> - the supported chips are mt2701 and mt8173.
> + the supported chips are mt2701, mt8173 and mt8183.
> - reg: Physical base address and length of the controller's registers
> - clocks: PLL reference clock
> - clock-output-names: name of the output clock line to the DSI encoder
> - #clock-cells: must be <0>;
> - #phy-cells: must be <0>.
>
> +Optional properties:
> +- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
> + unspecified default values shall be used.
> +- nvmem-cell-names: Should be "calibration-data"
> +- mipitx-current-drive: adjust driving current, should be 1 ~ 0xF
> +
> Example:
>
> mipi_tx0: mipi-dphy@10215000 {
> compatible = "mediatek,mt8173-mipi-tx";
> reg = <0 0x10215000 0 0x1000>;
> clocks = <&clk26m>;
> - clock-output-names = "mipi_tx0_pll";
> #clock-cells = <0>;
> #phy-cells = <0>;
> + clock-output-names = "mipi_tx0_pll";
> + nvmem-cells= <&mipi_tx_calibration>;
> + nvmem-cell-names = "calibration-data";
> + mipitx-current-drive = <0x8>;
> };
>
> dsi0: dsi@1401b000 {
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next prev parent reply other threads:[~2019-09-23 5:36 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-20 9:04 [PATCH v7 0/5] Support mipitx for mt8183 Jitao Shi
2019-09-20 9:04 ` [PATCH v7 1/5] dt-bindings: display: mediatek: update dsi supported chips Jitao Shi
2019-09-23 5:36 ` CK Hu [this message]
2019-09-27 1:34 ` CK Hu
2019-09-20 9:04 ` [PATCH v7 2/5] drm/mediatek: separate mipi_tx to different file Jitao Shi
2019-09-20 9:04 ` [PATCH v7 3/5] drm/mediatek: add mipi_tx driver for mt8183 Jitao Shi
2019-09-26 9:06 ` CK Hu
2019-09-20 9:04 ` [PATCH v7 4/5] drm/mediatek: add the mipitx driving control in device tree Jitao Shi
2019-09-20 9:04 ` [PATCH v7 5/5] drm/mediatek: config mipitx impedance with calibration data Jitao Shi
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