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Tue, 30 Jun 2020 02:54:29 -0800 Received: from MTKMBS01N2.mediatek.inc (172.21.101.79) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 30 Jun 2020 03:54:31 -0700 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 30 Jun 2020 18:54:17 +0800 Received: from [10.15.20.246] (10.15.20.246) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 30 Jun 2020 18:54:16 +0800 Message-ID: <1593514398.2581.7.camel@mbjsdccf07> Subject: Re: [PATCH v5 04/10] iommu/mediatek: Setting MISC_CTRL register From: chao hao To: Matthias Brugger Date: Tue, 30 Jun 2020 18:53:18 +0800 In-Reply-To: <0e9ceba8-0cc4-44a1-148c-1c9a6b3844ce@gmail.com> References: <20200629071310.1557-1-chao.hao@mediatek.com> <20200629071310.1557-5-chao.hao@mediatek.com> <0e9ceba8-0cc4-44a1-148c-1c9a6b3844ce@gmail.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: BAF6CEB1E06926B691EB2968E120FA304DAE48B58E1A3A76D8C81A49D6E53EB22000:8 X-MTK: N X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, FY Yang , wsd_upstream@mediatek.com, Joerg Roedel , linux-kernel@vger.kernel.org, Evan Green , Chao Hao , iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Yong Wu Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Mon, 2020-06-29 at 11:28 +0200, Matthias Brugger wrote: > > On 29/06/2020 09:13, Chao Hao wrote: > > Add F_MMU_IN_ORDER_WR_EN and F_MMU_STANDARD_AXI_MODE_BIT definition > > in MISC_CTRL register. > > F_MMU_STANDARD_AXI_MODE_BIT: > > If we set F_MMU_STANDARD_AXI_MODE_BIT(bit[3][19] = 0, not follow > > standard AXI protocol), iommu will send urgent read command firstly > > compare with normal read command to improve performance. > > Can you please help me to understand the phrase. Sorry I'm not a AXI specialist. > Does this mean that you will send a 'urgent read command' which is not described > in the specifications instead of a normal read command? ok. iommu sends read command to next bus_node normally(we can name it to cmd1), when cmd1 isn't handled by next bus_node, iommu has a urgent read command is needed to be sent(we can name it to cmd2), iommu will send cmd2 and replace cmd1. So cmd2 is handled by next bus_node firstly and cmd2 will be handled secondly. But for standard AXI protocol, it will ignore the priority of read command and only be handled in order. So cmd2 is handled by next bus_node after cmd1 is done. > > > F_MMU_IN_ORDER_WR_EN: > > If we set F_MMU_IN_ORDER_WR_EN(bit[1][17] = 0, out-of-order write), iommu > > will re-order write command and send more higher priority write command > > instead of sending write command in order. The feature be controlled > > by OUT_ORDER_EN macro definition. > > > > Cc: Matthias Brugger > > Suggested-by: Yong Wu > > Signed-off-by: Chao Hao > > --- > > drivers/iommu/mtk_iommu.c | 12 +++++++++++- > > drivers/iommu/mtk_iommu.h | 1 + > > 2 files changed, 12 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > > index 8f81df6cbe51..67b46b5d83d9 100644 > > --- a/drivers/iommu/mtk_iommu.c > > +++ b/drivers/iommu/mtk_iommu.c > > @@ -42,6 +42,9 @@ > > #define F_INVLD_EN1 BIT(1) > > > > #define REG_MMU_MISC_CTRL 0x048 > > +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) > > +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) > > Wouldn't it make more sense to name it F_MMU_STANDARD_AXI_MODE_EN? ok, you are right. 1'b1: follow standard axi protocol > > > + > > #define REG_MMU_DCM_DIS 0x050 > > > > #define REG_MMU_CTRL_REG 0x110 > > @@ -574,10 +577,17 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > > } > > writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > > > > + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); > > We only need to read regval in the else branch. ok, I got it. thanks > > > if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { > > /* The register is called STANDARD_AXI_MODE in this case */ > > - writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); > > + regval = 0; > > + } else { > > + /* For mm_iommu, it can improve performance by the setting */ > > + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; > > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_EN)) > > + regval &= ~F_MMU_IN_ORDER_WR_EN; > > } > > + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); > > > > if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, > > dev_name(data->dev), (void *)data)) { > > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > > index 7cc39f729263..4b780b651ef4 100644 > > --- a/drivers/iommu/mtk_iommu.h > > +++ b/drivers/iommu/mtk_iommu.h > > @@ -22,6 +22,7 @@ > > #define HAS_BCLK BIT(1) > > #define HAS_VLD_PA_RNG BIT(2) > > #define RESET_AXI BIT(3) > > +#define OUT_ORDER_EN BIT(4) > > Maybe something like OUT_ORDER_WR_EN, to make clear that it's about the the > write path. > ok, thanks for your advice. > > > > #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > > ((((pdata)->flags) & (_x)) == (_x)) > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek