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Thu, 20 Aug 2020 20:47:20 -0800 Received: from MTKMBS02N2.mediatek.inc (172.21.101.101) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 20 Aug 2020 21:47:18 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 21 Aug 2020 12:47:10 +0800 Received: from [172.21.77.33] (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 21 Aug 2020 12:47:10 +0800 Message-ID: <1597985231.23380.22.camel@mtkswgap22> Subject: Re: [PATCH v1 1/2] pinctrl: mediatek: support access registers without race-condition From: Light Hsieh To: Sean Wang Date: Fri, 21 Aug 2020 12:47:11 +0800 In-Reply-To: References: <1597739776-15944-1-git-send-email-light.hsieh@mediatek.com> X-Mailer: Evolution 3.2.3-0ubuntu6 MIME-Version: 1.0 X-TM-SNTS-SMTP: 51BC122EDEF3F1D67EED8335CAD5141E90041D04EFD83219FE1A1A71628C7C8B2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200821_004728_782382_32D46037 X-CRM114-Status: GOOD ( 37.34 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:GPIO SUBSYSTEM" , Linus Walleij , "moderated list:ARM/Mediatek SoC support" , lkml , kuohong.wang@mediatek.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Wed, 2020-08-19 at 16:11 -0700, Sean Wang wrote: > Hi Light, > > On Tue, Aug 18, 2020 at 1:36 AM wrote: > > > > From: Light Hsieh > > > > Some MediaTek SOC provide more control registers other than value register. > > s/MT6765/Some MediaTek SoC/ > > > Generanll, a value register need read-modify-write is at offset 0xXXXXXXXX0. > > s/Generally/Generanll/ > > > A corresponding SET register is at offset 0xXXXXXXX4. Write 1s' to some bits > > of SET register will set same bits in value register. > > A corresponding CLR register is at offset 0xXXXXXXX8. Write 1s' to some bits > > of CLR register will clear same bits in value register. > > For GPIO mode selection, MWR register is provided at offset 0xXXXXXXXC. > > With MWR, the MSBit of GPIO mode selection field is for modification-enable, > > not for GPIO mode selection, and the remaining LSBits are for mode > > selection. > > Take mode selection field with 4-bits as example, to select mode 0~7 via > > MWR register, 8~15 (instead of 0~7) shall be written to corresponding mode > > selection field. > > When using SET/CLR/MWR registers, read-modify-write of value register is not > > necessary. This can prevent from race condition when multiple bus masters > > concurrently read-modify-write the same value register for setting different > > fields of the same value register. > > > > Signed-off-by: Light Hsieh > > --- > > drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 69 ++++++++++++++++++++++-- > > drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h | 2 + > > 2 files changed, 67 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c > > index b77b18f..51f0b53 100644 > > --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c > > +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c > > @@ -18,6 +18,29 @@ > > #include "mtk-eint.h" > > #include "pinctrl-mtk-common-v2.h" > > > > +/* Some MediaTek SOC provide more control registers other than value register. > > s/MT6765/Some MediaTek SoC/ Not only MT6765 provides such control registers. Actually, many (but not all) MediaTek SoC support. Other MediaTek SoC can enable such control according to its HW support. > > > + * Generanll, a value register need read-modify-write is at offset 0xXXXXXXXX0. > > s/Generally/Generanll/ > > > + * A corresponding SET register is at offset 0xXXXXXXX4. Write 1s' to some bits > > + * of SET register will set same bits in value register. > > + * A corresponding CLR register is at offset 0xXXXXXXX8. Write 1s' to some bits > > + * of CLR register will clear same bits in value register. > > + * For GPIO mode selection, MWR register is provided at offset 0xXXXXXXXC. > > + * With MWR, the MSBit of GPIO mode selection field is for modification-enable, > > + * not for GPIO mode selection, and the remaining LSBits are for mode > > + * selection. > > + * Take mode selection field with 4-bits as example, to select mode 0~7 via > > + * MWR register, 8~15 (instead of 0~7) shall be written to corresponding mode > > + * selection field. > > + * When using SET/CLR/MWR registers, read-modify-write of value register is not > > + * necessary. This can prevent from race condition when multiple bus masters > > + * concurrently read-modify-write the same value register for setting different > > + * fields of the same value register. > > + */ > > + > > +#define SET_OFFSET 0x4 > > +#define CLR_OFFSET 0x8 > > can set/clr offset work for mode register? Yes. However, use set/clr to change mode require 2 register access when target mode is not all 0's or all 1's. The mwr HW support is not available on mode register. > > > +#define MWR_OFFSET 0xC > > + > > /** > > * struct mtk_drive_desc - the structure that holds the information > > * of the driving current > > @@ -64,6 +87,38 @@ void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set) > > mtk_w32(pctl, i, reg, val); > > } > > > > + > > +static void mtk_hw_set_value_race_free(struct mtk_pinctrl *pctl, > > + struct mtk_pin_field *pf, u32 value) > > s/mtk_hw_set_value_race_free/mtk_hw_w1sc/ to explictly indicate > write-one ethier set or clear operation supported by hw > > > +{ > > + unsigned int set, clr; > > + > > + set = value & pf->mask; > > + clr = (~set) & pf->mask; > > + > > + if (set) > > + mtk_w32(pctl, pf->index, pf->offset + SET_OFFSET, > > + set << pf->bitpos); > > + if (clr) > > + mtk_w32(pctl, pf->index, pf->offset + CLR_OFFSET, > > + clr << pf->bitpos); > > +} > > + > > +static void mtk_hw_set_mode_race_free(struct mtk_pinctrl *pctl, > > + struct mtk_pin_field *pf, u32 value) > > s/mtk_hw_set_mode_race_free/mtk_hw_mwr/ > > > +{ > > + unsigned int value_new; > > + > > + /* MSB of mask is modification-enable bit, set this bit */ > > + value_new = (1 << (pctl->soc->mwr_field_width - 1)) | value; > > it seems to be we can use fls(pf->mask) to replace ctl->soc->mwr_field_width > pf->mask cannot be used direct. It needs conversion.For example: pf->mask: 0x1f -> value_new = (1 << 4) | value; pf->mask: 0xf -> value_new = (1 << 3) | value; pf->mask: 0x7 -> value_new = (1 << 2) | value; The code size of perform conversion is greater than using a direct mwr_field_width field. > > + if (value_new == value) > > + dev_notice(pctl->dev, > > + "invalid mode 0x%x, use it by ignoring MSBit!\n", > > + value); > > + mtk_w32(pctl, pf->index, pf->offset + MWR_OFFSET, > > + value_new << pf->bitpos); > > +} > > + > > static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, > > const struct mtk_pin_desc *desc, > > int field, struct mtk_pin_field *pfd) > > @@ -197,10 +252,16 @@ int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, > > if (value < 0 || value > pf.mask) > > return -EINVAL; > > > > - if (!pf.next) > > - mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos, > > - (value & pf.mask) << pf.bitpos); > > - else > > + if (!pf.next) { > > + if (hw->soc->race_free_access) { > > let's create an extra flags caps under hw->soc and the SoC capability > check, something like hw->soc->caps & MTK_HW_CAPS_RMW_ATOMIC to easily > extend various things for future SoC > > > + if (field == PINCTRL_PIN_REG_MODE) > > + mtk_hw_set_mode_race_free(hw, &pf, value); > > + else > > + mtk_hw_set_value_race_free(hw, &pf, value); > > + } > > let's create a function holding that specific hardware stuff (at least > currently it look like), something like > > static void mtk_hw_rmw(struct mtk_pinctrl *pctl, struct mtk_pin_field *pf) > { > if (pf->field == PINCTRL_PIN_REG_MODE) /* create a member field for pf */ > mtk_hw_mwr(...); > else > mtk_hw_w1sc(...); > } > Sine there is no member 'field' in struct mtk_pin_field, pf->field cannot be used. Therefore an extra function parameter is required if you want to use a standalone function mtk_hw_rmw. Like this: void mtk_hw_rmw(struct mtk_pinctrl *pctl, struct mtk_pin_field *pf, int field, u32 value) { if (field == PINCTRL_PIN_REG_MODE) mtk_hw_set_mode_race_free(hw, &pf, value); else mtk_hw_set_value_race_free(hw, &pf, value); } I wonder the necessity/efficiency of such extra intermediate function with many function parameters. > > + mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos, > > + (value & pf.mask) << pf.bitpos); > > + } else > > mtk_hw_write_cross_field(hw, &pf, value); > > > > return 0; > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h > > index 27df087..95fb329 100644 > > --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h > > +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h > > @@ -203,6 +203,8 @@ struct mtk_pin_soc { > > /* Specific parameters per SoC */ > > u8 gpio_m; > > bool ies_present; > > + bool race_free_access; > > + unsigned int mwr_field_width; > > const char * const *base_names; > > unsigned int nbase_names; > > > > -- > > 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek