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Wed, 09 Dec 2020 23:09:28 -0800 Received: from MTKMBS06N1.mediatek.inc (172.21.101.129) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 9 Dec 2020 23:01:10 -0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs06n1.mediatek.inc (172.21.101.129) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 10 Dec 2020 15:01:09 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 10 Dec 2020 15:01:09 +0800 Message-ID: <1607583669.2269.2.camel@mtksdaap41> Subject: Re: [PATCH 3/3] arm64: dts: mt8183: Add display nodes for MT8183 From: CK Hu To: Enric Balletbo i Serra Date: Thu, 10 Dec 2020 15:01:09 +0800 In-Reply-To: <20201127104930.1981497-4-enric.balletbo@collabora.com> References: <20201127104930.1981497-1-enric.balletbo@collabora.com> <20201127104930.1981497-4-enric.balletbo@collabora.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201210_020938_105967_8170325F X-CRM114-Status: GOOD ( 14.08 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , Collabora Kernel ML , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi, Enric: On Fri, 2020-11-27 at 11:49 +0100, Enric Balletbo i Serra wrote: > Add display subsystem device nodes to allow video output. > > Signed-off-by: Enric Balletbo i Serra > --- > > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 114 +++++++++++++++++++++++ > 1 file changed, 114 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index ba9ff192cda3..34d83f517b07 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -6,6 +6,7 @@ > */ > > #include > +#include This should be #include Regards, CK > #include > #include > #include > @@ -33,6 +34,11 @@ aliases { > i2c9 = &i2c9; > i2c10 = &i2c10; > i2c11 = &i2c11; > + ovl0 = &ovl0; > + ovl-2l0 = &ovl_2l0; > + ovl-2l1 = &ovl_2l1; > + rdma0 = &rdma0; > + rdma1 = &rdma1; > }; > > cpus { > @@ -964,6 +970,107 @@ mmsys: syscon@14000000 { > #clock-cells = <1>; > }; > > + ovl0: ovl@14008000 { > + compatible = "mediatek,mt8183-disp-ovl"; > + reg = <0 0x14008000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL0>; > + iommus = <&iommu M4U_PORT_DISP_OVL0>; > + mediatek,larb = <&larb0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; > + }; > + > + ovl_2l0: ovl@14009000 { > + compatible = "mediatek,mt8183-disp-ovl-2l"; > + reg = <0 0x14009000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > + iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; > + mediatek,larb = <&larb0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; > + }; > + > + ovl_2l1: ovl@1400a000 { > + compatible = "mediatek,mt8183-disp-ovl-2l"; > + reg = <0 0x1400a000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; > + iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; > + mediatek,larb = <&larb0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; > + }; > + > + rdma0: rdma@1400b000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400b000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > + iommus = <&iommu M4U_PORT_DISP_RDMA0>; > + mediatek,larb = <&larb0>; > + mediatek,rdma_fifo_size = <5120>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; > + }; > + > + rdma1: rdma@1400c000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + iommus = <&iommu M4U_PORT_DISP_RDMA1>; > + mediatek,larb = <&larb0>; > + mediatek,rdma_fifo_size = <2048>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; > + }; > + > + color0: color@1400e000 { > + compatible = "mediatek,mt8183-disp-color", > + "mediatek,mt8173-disp-color"; > + reg = <0 0x1400e000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_COLOR0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; > + }; > + > + ccorr0: ccorr@1400f000 { > + compatible = "mediatek,mt8183-disp-ccorr"; > + reg = <0 0x1400f000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_CCORR0>; > + }; > + > + aal0: aal@14010000 { > + compatible = "mediatek,mt8183-disp-aal", > + "mediatek,mt8173-disp-aal"; > + reg = <0 0x14010000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_AAL0>; > + }; > + > + gamma0: gamma@14011000 { > + compatible = "mediatek,mt8183-disp-gamma", > + "mediatek,mt8173-disp-gamma"; > + reg = <0 0x14011000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; > + }; > + > + dither0: dither@14012000 { > + compatible = "mediatek,mt8183-disp-dither"; > + reg = <0 0x14012000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_DITHER0>; > + }; > + > dsi0: dsi@14014000 { > compatible = "mediatek,mt8183-dsi"; > reg = <0 0x14014000 0 0x1000>; > @@ -978,6 +1085,13 @@ dsi0: dsi@14014000 { > phy-names = "dphy"; > }; > > + mutex: mutex@14016000 { > + compatible = "mediatek,mt8183-disp-mutex"; > + reg = <0 0x14016000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + }; > + > larb0: larb@14017000 { > compatible = "mediatek,mt8183-smi-larb"; > reg = <0 0x14017000 0 0x1000>; _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek