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Tue, 22 Dec 2020 16:43:20 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 22 Dec 2020 16:33:18 -0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 23 Dec 2020 08:33:17 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 23 Dec 2020 08:33:11 +0800 Message-ID: <1608683595.18252.0.camel@mhfsdcap03> Subject: Re: [PATCH v1, 3/5] mailbox: mediatek: add control_by_sw private data From: Yongqiang Niu To: Nicolas Boichat Date: Wed, 23 Dec 2020 08:33:15 +0800 In-Reply-To: References: <1607141728-17307-1-git-send-email-yongqiang.niu@mediatek.com> <1607141728-17307-4-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201222_194334_613056_5714E652 X-CRM114-Status: GOOD ( 19.41 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Yongqiang Niu Cc: Jassi Brar , lkml , Dennis YC Hsieh , CK Hu , Rob Herring , "moderated list:ARM/Mediatek SoC support" , Bibby Hsieh , Matthias Brugger , linux-arm Mailing List Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Sat, 2020-12-05 at 15:35 +0800, Nicolas Boichat wrote: > On Sat, Dec 5, 2020 at 12:18 PM Yongqiang Niu > wrote: > > > > add control_by_sw private data > > Can you describe in a bit more details what this means? gce works well without this patch, and it will be removed in next version > > > > > Signed-off-by: Yongqiang Niu > > --- > > drivers/mailbox/mtk-cmdq-mailbox.c | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c > > index 5665b6e..1c01fe0 100644 > > --- a/drivers/mailbox/mtk-cmdq-mailbox.c > > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c > > @@ -36,6 +36,8 @@ > > #define CMDQ_THR_WAIT_TOKEN 0x30 > > #define CMDQ_THR_PRIORITY 0x40 > > > > +#define GCE_GCTL_VALUE 0x48 > > + > > #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 > > #define CMDQ_THR_ENABLED 0x1 > > #define CMDQ_THR_DISABLED 0x0 > > @@ -76,11 +78,13 @@ struct cmdq { > > struct clk *clock; > > bool suspended; > > u8 shift_pa; > > + bool control_by_sw; > > }; > > > > struct gce_plat { > > u32 thread_nr; > > u8 shift; > > + bool control_by_sw; > > }; > > > > u8 cmdq_get_shift_pa(struct mbox_chan *chan) > > @@ -121,6 +125,8 @@ static void cmdq_init(struct cmdq *cmdq) > > int i; > > > > WARN_ON(clk_enable(cmdq->clock) < 0); > > + if (cmdq->control_by_sw) > > + writel(0x7, cmdq->base + GCE_GCTL_VALUE); > > What is 0x7? Define a macro for these bits? > > > writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); > > for (i = 0; i <= CMDQ_MAX_EVENT; i++) > > writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); > > @@ -536,6 +542,7 @@ static int cmdq_probe(struct platform_device *pdev) > > > > cmdq->thread_nr = plat_data->thread_nr; > > cmdq->shift_pa = plat_data->shift; > > + cmdq->control_by_sw = plat_data->control_by_sw; > > cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); > > err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, > > "mtk_cmdq", cmdq); > > -- > > 1.8.1.1.dirty > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek