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Wed, 12 May 2021 08:59:11 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 354EC61400; Wed, 12 May 2021 08:59:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1620809949; bh=VYEJFMS0hse+hUR69F2l8nW24uqubwgMP3YYvib8gYA=; h=Subject:To:Cc:From:Date:From; b=IYVEcvsQUPceduvBeLrEaU2+xwS0p+LweGsSbaLAMYVHjlmIHwJc1aJzLKKwAznuc SUrk7mR5FGRHs8TLte8o6CTgRuv2h+AiAtBn8aq00sr4tYVJB8MJ2bHoFrxmvKLj9n GJYUAR+xaOpmVqZ/fIo4ZYjWD878wCqnoS3EUwJs= Subject: Patch "MIPS: pci-mt7620: fix PLL lock check" has been added to the 5.10-stable tree To: gregkh@linuxfoundation.org, ilya.lipnitskiy@gmail.com, john@phrozen.org, linux-mediatek@lists.infradead.org, tsbogend@alpha.franken.de Cc: From: Date: Wed, 12 May 2021 10:57:53 +0200 Message-ID: <162080987326148@kroah.com> MIME-Version: 1.0 X-stable: commit X-Patchwork-Hint: ignore X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210512_015910_505666_19B6D3A3 X-CRM114-Status: GOOD ( 14.79 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org This is a note to let you know that I've just added the patch titled MIPS: pci-mt7620: fix PLL lock check to the 5.10-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: mips-pci-mt7620-fix-pll-lock-check.patch and it can be found in the queue-5.10 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >From c15b99ae2ba9ea30da3c7cd4765b8a4707e530a6 Mon Sep 17 00:00:00 2001 From: Ilya Lipnitskiy Date: Sat, 6 Mar 2021 20:17:24 -0800 Subject: MIPS: pci-mt7620: fix PLL lock check From: Ilya Lipnitskiy commit c15b99ae2ba9ea30da3c7cd4765b8a4707e530a6 upstream. Upstream a long-standing OpenWrt patch [0] that fixes MT7620 PCIe PLL lock check. The existing code checks the wrong register bit: PPLL_SW_SET is not defined in PPLL_CFG1 and bit 31 of PPLL_CFG1 is marked as reserved in the MT7620 Programming Guide. The correct bit to check for PLL lock is PPLL_LD (bit 23). Also reword the error message for clarity. Without this change it is unlikely that this driver ever worked with mainline kernel. [0]: https://lists.infradead.org/pipermail/lede-commits/2017-July/004441.html Signed-off-by: Ilya Lipnitskiy Cc: John Crispin Cc: linux-mips@vger.kernel.org Cc: linux-mediatek@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org Signed-off-by: Thomas Bogendoerfer Signed-off-by: Greg Kroah-Hartman --- arch/mips/pci/pci-mt7620.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) --- a/arch/mips/pci/pci-mt7620.c +++ b/arch/mips/pci/pci-mt7620.c @@ -30,6 +30,7 @@ #define RALINK_GPIOMODE 0x60 #define PPLL_CFG1 0x9c +#define PPLL_LD BIT(23) #define PPLL_DRV 0xa0 #define PDRV_SW_SET BIT(31) @@ -239,8 +240,8 @@ static int mt7620_pci_hw_init(struct pla rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1); mdelay(100); - if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) { - dev_err(&pdev->dev, "MT7620 PPLL unlock\n"); + if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) { + dev_err(&pdev->dev, "pcie PLL not locked, aborting init\n"); reset_control_assert(rstpcie0); rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1); return -1; Patches currently in stable-queue which might be from ilya.lipnitskiy@gmail.com are queue-5.10/mips-pci-mt7620-fix-pll-lock-check.patch queue-5.10/mips-pci-rt2880-fix-slot-0-configuration.patch _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek