From mboxrd@z Thu Jan 1 00:00:00 1970 From: Weiyi Lu Subject: [resend PATCH v1 1/2] dt-bindings: clock: add clock for MT2712 Date: Fri, 14 Dec 2018 10:04:16 +0800 Message-ID: <20181214020417.2871-3-weiyi.lu@mediatek.com> References: <20181214020417.2871-1-weiyi.lu@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <20181214020417.2871-1-weiyi.lu@mediatek.com> Sender: linux-kernel-owner@vger.kernel.org To: Matthias Brugger , Stephen Boyd , Rob Herring Cc: James Liao , Fan Chen , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, srv_heupstream@mediatek.com, Weiyi Lu List-Id: linux-mediatek@lists.infradead.org Add new clock according to 3rd ECO design change. It's the parent clock of audio clock mux. Signed-off-by: Weiyi Lu --- include/dt-bindings/clock/mt2712-clk.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/mt2712-clk.h b/include/dt-bindings/clock/mt2712-clk.h index 76265836a1e1..c3b29dff9c0e 100644 --- a/include/dt-bindings/clock/mt2712-clk.h +++ b/include/dt-bindings/clock/mt2712-clk.h @@ -228,7 +228,8 @@ #define CLK_TOP_NFI2X_EN 189 #define CLK_TOP_NFIECC_EN 190 #define CLK_TOP_NFI1X_CK_EN 191 -#define CLK_TOP_NR_CLK 192 +#define CLK_TOP_APLL2_D3 192 +#define CLK_TOP_NR_CLK 193 /* INFRACFG */ -- 2.18.0