From: wangyan wang <wangyan.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
To: wangyan wang <wangyan.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Cc: Ryder Lee <ryder.lee-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
chunhui dai <chunhui.dai-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Subject: [PATCH V4 4/8] drm/mediatek: fix the rate and divder of hdmi phy for MT2701
Date: Tue, 19 Feb 2019 17:31:11 +0800 [thread overview]
Message-ID: <20190219093115.16449-5-wangyan.wang@mediatek.com> (raw)
In-Reply-To: <20190219093115.16449-1-wangyan.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
From: chunhui dai <chunhui.dai-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Due to a clerical error,there is one zero less for 12800000.
Fix it for 128000000.
Fixes: 0fc721b2968e ("drm/mediatek: add hdmi driver for MT2701 and MT7623")
Reviewed-by: CK Hu <ck.hu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Signed-off-by: chunhui dai <chunhui.dai-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Signed-off-by: wangyan wang <wangyan.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
index 43bc058d5528..88dd9e812ca0 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
@@ -114,8 +114,8 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
if (rate <= 64000000)
pos_div = 3;
- else if (rate <= 12800000)
- pos_div = 1;
+ else if (rate <= 128000000)
+ pos_div = 2;
else
pos_div = 1;
--
2.14.1
next prev parent reply other threads:[~2019-02-19 9:31 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-19 9:31 [PATCH V4 0/8] make mt7623 clock of hdmi stable wangyan wang
[not found] ` <20190219093115.16449-1-wangyan.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2019-02-19 9:31 ` [PATCH v4 1/8] drm/mediatek: recalculate hdmi phy clock of MT2701 by querying hardware wangyan wang
2019-02-19 9:31 ` [PATCH V4 2/8] drm/mediatek: move the setting of fixed divider wangyan wang
2019-02-19 9:31 ` [PATCH V4 3/8] drm/mediatek: using different flags of clk for HDMI phy wangyan wang
2019-02-19 9:31 ` wangyan wang [this message]
2019-02-19 9:31 ` [PATCH V4 5/8] clk: mediatek: add MUX_GATE_FLAGS_2 wangyan wang
2019-02-19 9:31 ` [PATCH V4 6/8] clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel wangyan wang
2019-02-19 9:31 ` [PATCH V4 7/8] drm/mediatek: using new factor for tvdpll in MT2701 wangyan wang
2019-02-19 9:31 ` [PATCH V4 8/8] drm/mediatek: fix the rate of parent for hdmi phy " wangyan wang
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