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From: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
To: <daniel@0x0f.com>, Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Cc: <daniel@thingy.jp>, <linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>, <matthias.bgg@gmail.com>,
	<maz@kernel.org>, <tglx@linutronix.de>, <yj.chiang@mediatek.com>
Subject: Re: [PATCH v2] irqchip/irq-mst: Support polarity configuration
Date: Mon, 15 Mar 2021 16:58:55 +0800	[thread overview]
Message-ID: <20210315085855.23730-1-mark-pk.tsai@mediatek.com> (raw)
In-Reply-To: <CAFr9PXmwp5FQP8dOZed0siz76qj4Lo-ytt=nt+1GR5qAFtEr9g@mail.gmail.com>

From: Daniel Palmer <daniel@0x0f.com>

> On Fri, 12 Mar 2021 at 01:11, Mark-PK Tsai <mark-pk.tsai@mediatek.com> wrote:
> > Why irq could accept either?
> 
> As the irq intc has no way to clear it's triggered state (no eoi) it
> must just pass the signal through instead of latching it?
> Otherwise it would latch once and never again right? That's what I
> really didn't understand.
> If it just passes the signal through and maybe inverts it then the GIC
> can use edge or level I think.

Yes, but if we accidentally loss a irq and the interrupt is edge triggered which is
latch to level by mst-intc, we will miss all the follow irqs because the driver
didn't reset the interrupt status.
Actually, I'm not sure if it's possible.
But even if it's not, I think use level for parent GIC can better match
the hardware signal processing.

> 
> > So maybe we don't need to do extra work to check the type for an fiq or irq controller?
> 
> I think without the eoi callback for the fiq it would only ever fire
> once. I don't think doing the same eoi callback for the irq intc hurts
> anything but it wouldn't do anything either from what I can tell.

The reason why I don't do the same eoi callback for irq intc is that
it's not ont spec.
And some of MTK TV SoC use it for certain debug function which
may cause unexpected result.

> 
> > And I will update the patch as following:
> 
> I think maybe Marc or someone else that knows better than I do should
> comment on what needs to happen.
> My input is just that the fiq controller seems to trigger on an edge,
> holds it's signal to the GIC high until eoi happens and then only
> triggers again on an edge.
> I guess it doesn't matter if it's an edge or level if that's how it
> works but you'd only get one interrupt out of it per edge even if
> configured as a level interrupt.
> 
> The main thing I didn't want was filtering out edge interrupts
> entirely as that breaks using edge interrupts with gpios i.e. using
> gpiomon.
> With the changes to set the polarity it can now detect rising or
> falling edge gpio events. :)

Thanks for your feedback and I will send patch v4 which includes the
change I proposed in this thread.
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      reply	other threads:[~2021-03-15  9:00 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-08  6:05 [PATCH v2] irqchip/irq-mst: Support polarity configuration Mark-PK Tsai
2021-03-08 13:40 ` Daniel Palmer
2021-03-08 14:30   ` Mark-PK Tsai
2021-03-10 10:20     ` Daniel Palmer
2021-03-11  3:12       ` Mark-PK Tsai
2021-03-11 12:33         ` Daniel Palmer
2021-03-11 16:11           ` Mark-PK Tsai
2021-03-12 10:35             ` Daniel Palmer
2021-03-15  8:58               ` Mark-PK Tsai [this message]

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