Re: [RFC,v1 0/4] Add a driver for Mediatek SPI Nand controller

[Miquel Raynal <miquel.raynal@bootlin.com>]

Hello,

xiangsheng.hou@mediatek.com wrote on Mon, 27 Sep 2021 13:36:25 +0800:

> Add a driver for Mediatek SPI Nand controller
> 
> Mediatek SPI Nand controller cosists of two parts: on-host HW ECC and
> snfi(stand for spi nand flash interface). They can cowork with high
> performance which called ECC nfi mode. The nfi stand for nand flash
> interfacei(snfi a one part of nfi) which can support SPI Nand flash
> and raw nand flash.
> 
> However, the snfi driver in spi subsytem need to be aware of nand
> parameter(page/spare size) and ecc status(enable/disable) when work
> at ECC nfi mode. The snfi driver in spi subsystem seems difficult to
> know these.
> 
> Therefore, consider two ways to let snfi can get these information.
> The RFC patch send to review whether they are suitable and which
> solution maybe better.
> 
> RFC patch v1:
> Add nfi register base at bch(ecc) dts node and config nand parameter
> and ecc status into nfi registers in ecc driver, then parse these
> information at snfi driver to use.
> 
> RFC patch v2:
> Export some function in HW ECC driver and snfi driver.
> In HW ECC driver, export function include get nand page/spare size, HW
> ECC status(enable/disable) and fdm(oob free per sector in ooblayout) size.
> In snfi driver need export empty page status which the nfi can be aware
> when in ECC nfi mode(the spim framework can not return this information).
> 

I've looked at both versions that you provided and I thought about a
number of things that cannot be done like this:
- I believe the snfi is a regular SPI controller. I will let Mark
  confirm but I do not think we want to start writing SPI-NAND
  controllers. Instead we write SPI controllers and we provide SPI-mem
  operations (we've explained this in a previous ELC, the video is
  available on YouTube).
- You cannot add an MTK ECC algorithm. This is dedicated for sofware
  solutions only and as far as I understand your engine uses the BCH
  algorithm.
- When the ECC engine is pipelined, there is an additional complexity
  in interfacing it with a SPI controller (that's your case I believe).
  I have an example that is not yet upstream but I think worth looking
  at that I will send very soon (I will Cc: you on it).
- The DT description for those engines that has been described on the
  mailing list and will be enforced is:

// External engine

	&spi-controller {
                flash@0 {
                        compatible = "spi-nand";
                        reg = <0>;
                        nand-ecc-engine = <&ecc_engine>;
                        spi-max-frequency = <50000000>;
                        spi-tx-bus-width = <4>;
                        spi-rx-bus-width = <4>;
                };
        };

        ecc_engine: ecc@43c40000 {
                compatible = "mxic,nand-ecc-engine-rev3";
                reg = <0x43c40000 0x10000>;
        };
 

// Pipelined engine

	&spi-controller {
               nand-ecc-engine = <&ecc_engine>;
 
                flash@0 {
                        compatible = "spi-nand";
                        reg = <0>;
                        nand-ecc-engine = <&spi_controller>;
                        spi-max-frequency = <50000000>;
                        spi-tx-bus-width = <4>;
                        spi-rx-bus-width = <4>;
 		};
	};

        ecc_engine: ecc@43c40000 {
                compatible = "mxic,nand-ecc-engine-rev3";
                reg = <0x43c40000 0x10000>;
        };

Thanks,
Miquèl

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