Re: [RFC,v1 0/4] Add a driver for Mediatek SPI Nand controller

[Miquel Raynal <miquel.raynal@bootlin.com>]

Hello,

xiangsheng.hou@mediatek.com wrote on Mon, 11 Oct 2021 19:31:28 +0800:

> Hi Miquel,
> 
> On Fri, 2021-10-08 at 11:20 +0200, Miquel Raynal wrote:
> > Hello,
> > 
> > xiangsheng.hou@mediatek.com wrote on Mon, 27 Sep 2021 13:36:25 +0800:
> >   
> > > Add a driver for Mediatek SPI Nand controller
> > > 
> > > Mediatek SPI Nand controller cosists of two parts: on-host HW ECC
> > > and
> > > snfi(stand for spi nand flash interface). They can cowork with high
> > > performance which called ECC nfi mode. The nfi stand for nand flash
> > > interfacei(snfi a one part of nfi) which can support SPI Nand flash
> > > and raw nand flash.
> > > 
> > > However, the snfi driver in spi subsytem need to be aware of nand
> > > parameter(page/spare size) and ecc status(enable/disable) when work
> > > at ECC nfi mode. The snfi driver in spi subsystem seems difficult
> > > to
> > > know these.
> > > 
> > > Therefore, consider two ways to let snfi can get these information.
> > > The RFC patch send to review whether they are suitable and which
> > > solution maybe better.
> > >   
> > 
> > I've looked at both versions that you provided and I thought about a
> > number of things that cannot be done like this:
> > - I believe the snfi is a regular SPI controller. I will let Mark
> >   confirm but I do not think we want to start writing SPI-NAND
> >   controllers. Instead we write SPI controllers and we provide SPI-
> > mem
> >   operations (we've explained this in a previous ELC, the video is
> >   available on YouTube).  
> 
> The snfi controller can support multiple SPI protocols, which can
> support other SPI device in theory. However, the snfi need to know nand
> parameter and ecc status(enable/disable) when work with MTK on-host HW
> BCH ECC engine for nand flash.
> 
> Therefore, the RFC patch v1/v2 is try the way to get these information.
> 
> > - You cannot add an MTK ECC algorithm. This is dedicated for sofware
> >   solutions only and as far as I understand your engine uses the BCH
> >   algorithm.
> > - When the ECC engine is pipelined, there is an additional complexity
> >   in interfacing it with a SPI controller (that's your case I
> > believe).
> >   I have an example tintendhat is not yet upstream but I think worth
> > looking
> >   at that I will send very soon (I will Cc: you on it).  
> 
> Thanks for your patch.
> 
> MTK HW ECC(bch) algorithm can work in pipelined and external.
> However, the performance worse when work at ecternal which realize and
> verify in local. Therefore, try the pipelined in RFC patch v1/v2.

Yes this is completely expected as the data must be moved twice instead
of once. I believe pipelined mode is harder to implement in software but
brings better performances.

> And also realize the mtd/nand info can be get in spi driver which the
> spi-mxic driver in your patch. This may solve most of difficulty that
> encountered in the snfi driver that the RFC patch v1/v2 try to resolve.

Great, that was indeed the goal.

> I will prepare the RFC patch v3 with correct pipelined ecc engine
> realization for your review.

Thanks,
Miquèl

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