Re: [PATCH v5 4/4] arm64: dts: mt8192: Add vcodec lat and core nodes

allen-kh.cheng
2022-04-01T05:06:50Z

Hi Matthias,

On Thu, 2022-03-31 at 16:09 +0200, Matthias Brugger wrote:
>
> On 30/03/2022 15:38, Allen-KH Cheng wrote:
> > Add vcodec lat and core nodes for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
>
> Please drop reviewed-by as of comments below.
>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60
> > ++++++++++++++++++++++++
> > 1 file changed, 60 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 3d61238fb102..0b2b52a8f5ed 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1115,6 +1115,66 @@
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_ISP2>;
> > };
> >
> > + vcodec_dec: vcodec-dec@16000000 {
> > + compatible = "mediatek,mt8192-vcodec-dec";
> > + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS
> > */
> > + mediatek,scp = <&scp>;
> > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0
> > 0xfff00000>;
>
> Change that was not part of the changelog. Please mention any change
> you make to
> the patch in the change log.
>
> > + #address-cells = <2>;
> > + #size-cells = <2>;
>
> Binding description says address-cells and size-cells should be of
> value 1.
>
>
> > + ranges = <0 0 0 0x16000000 0 0x26000>;
> > +
> > + vcodec_lat: vcodec-lat@10000 {
> > + compatible = "mediatek,mtk-vcodec-lat";
> > + reg = <0x0 0x10000 0 0x800>;
> > /* VDEC_MISC */
>
> I suppose we would need to fix the reg value here then. Also IMHO the
> comment
> can be deleted.
>

vcodec_dec: vcodec-dec@16000000 {
compatible = "mediatek,mt8192-
vcodec-dec";
reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */

mediatek,scp = <&scp>;
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;

dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
#address-cells
= <1>;
#size-cells = <1>;
ranges = <0 0 0x16000000 0x26000>;

vcodec_lat: vcodec-lat@10000 {
compatible = "mediatek,mtk-vcodec-
lat";
reg = <0x10000 0x800>;

Just want to confirm.

As shown above, is that correct?

Thanks,
Allen

> > + interrupts = <GIC_SPI 426
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > + iommus = <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > + <&vdecsys_soc
> > CLK_VDEC_SOC_VDEC>,
> > + <&vdecsys_soc
> > CLK_VDEC_SOC_LAT>,
> > + <&vdecsys_soc
> > CLK_VDEC_SOC_LARB1>,
> > + <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + clock-names = "sel", "soc-vdec", "soc-
> > lat", "vdec", "top";
> > + assigned-clocks = <&topckgen
> > CLK_TOP_VDEC_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC>;
> > + };
> > +
> > + vcodec_core: vcodec-core@25000 {
> > + compatible = "mediatek,mtk-vcodec-
> > core";
> > + reg = <0 0x25000 0 0x1000>; /*
> > VDEC_CORE_MISC */
>
> same here.
>
> Regards,
> Matthias
>
> > + interrupts = <GIC_SPI 425
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > + iommus = <&iommu0
> > M4U_PORT_L4_VDEC_MC_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_UFO_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_PP_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_TILE_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_VLD_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_VLD2_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > + <&vdecsys CLK_VDEC_VDEC>,
> > + <&vdecsys CLK_VDEC_LAT>,
> > + <&vdecsys CLK_VDEC_LARB1>,
> > + <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + clock-names = "sel", "soc-vdec", "soc-
> > lat", "vdec", "top";
> > + assigned-clocks = <&topckgen
> > CLK_TOP_VDEC_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC2>;
> > + };
> > + };
> > +
> > larb5: larb@1600d000 {
> > compatible = "mediatek,mt8192-smi-larb";
> > reg = <0 0x1600d000 0 0x1000>;