[PATCH V4 15/15] arm64: dts: mediatek: Add infra #reset-cells property for MT8195

Rex-BC Chen
2022-04-27T03:14:18Z

We will use mediatek clock reset as infracfg_ao reset instead of ti-syscon.
To support this, remove the property of ti reset and add the property of
#reset-cells for mediatek clock reset.

Fixes: 4c78814a1f46ac0 (arm64: dts: Add mediatek SoC mt8195 and evaluation board)
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index b57e620c2c72..8e5ac11b19f1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -10,7 +10,6 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
-#include <dt-bindings/reset/ti-syscon.h>

/ {
compatible = "mediatek,mt8195";
@@ -295,17 +294,7 @@
compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
-
- infracfg_rst: reset-controller {
- compatible = "ti,syscon-reset";
- #reset-cells = <1>;
- ti,reset-bits = <
- 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */
- 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
- 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
- 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */
- >;
- };
+ #reset-cells = <1>;
};

pericfg: syscon@10003000 {