* [PATCH 1/4] arm64: dts: mt8195: Add dp-intf nodes
2022-09-15 7:58 [PATCH 0/4] Add dp-intf and dp nodes Bo-Chen Chen
@ 2022-09-15 7:58 ` Bo-Chen Chen
2022-09-15 8:13 ` AngeloGioacchino Del Regno
2022-09-15 7:58 ` [PATCH 2/4] arm64: dts: mt8195: Add dptx nodes Bo-Chen Chen
` (2 subsequent siblings)
3 siblings, 1 reply; 11+ messages in thread
From: Bo-Chen Chen @ 2022-09-15 7:58 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt
Cc: matthias.bgg, angelogioacchino.delregno, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Bo-Chen Chen
Add dp-intf0 and dp-intf1 nodes for MT8195.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 905d1a90b406..93e6a106a9b8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -2155,5 +2155,28 @@
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
};
+
+ dp_intf0: dp-intf@1c015000 {
+ status = "disabled";
+ compatible = "mediatek,mt8195-dp-intf";
+ reg = <0 0x1c015000 0 0x1000>;
+ interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys0 CLK_VDO0_DP_INTF0>,
+ <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+ <&apmixedsys CLK_APMIXED_TVDPLL1>;
+ clock-names = "engine", "pixel", "pll";
+ };
+
+ dp_intf1: dp-intf@1c113000 {
+ compatible = "mediatek,mt8195-dp-intf";
+ reg = <0 0x1c113000 0 0x1000>;
+ interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
+ <&vdosys1 CLK_VDO1_DPINTF>,
+ <&apmixedsys CLK_APMIXED_TVDPLL2>;
+ clock-names = "engine", "pixel", "pll";
+ status = "disabled";
+ };
};
};
--
2.18.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 1/4] arm64: dts: mt8195: Add dp-intf nodes
2022-09-15 7:58 ` [PATCH 1/4] arm64: dts: mt8195: Add dp-intf nodes Bo-Chen Chen
@ 2022-09-15 8:13 ` AngeloGioacchino Del Regno
2022-09-15 8:32 ` Bo-Chen Chen
0 siblings, 1 reply; 11+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-15 8:13 UTC (permalink / raw)
To: Bo-Chen Chen, robh+dt, krzysztof.kozlowski+dt
Cc: matthias.bgg, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Project_Global_Chrome_Upstream_Group
Il 15/09/22 09:58, Bo-Chen Chen ha scritto:
> Add dp-intf0 and dp-intf1 nodes for MT8195.
>
> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 905d1a90b406..93e6a106a9b8 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -2155,5 +2155,28 @@
> clock-names = "apb", "smi", "gals";
> power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> };
> +
> + dp_intf0: dp-intf@1c015000 {
Please keep the devicetree nodes ordered by mmio.
dp_intf0 goes between mutex@1c016000 and larb@1c018000.
> + status = "disabled";
status = "disabled" across the entire mt8195.dtsi nodes is always at the end.
Please keep consistency.
> + compatible = "mediatek,mt8195-dp-intf";
> + reg = <0 0x1c015000 0 0x1000>;
> + interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys0 CLK_VDO0_DP_INTF0>,
> + <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
> + <&apmixedsys CLK_APMIXED_TVDPLL1>;
> + clock-names = "engine", "pixel", "pll";
> + };
> +
> + dp_intf1: dp-intf@1c113000 {
> + compatible = "mediatek,mt8195-dp-intf";
> + reg = <0 0x1c113000 0 0x1000>;
> + interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> + clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
> + <&vdosys1 CLK_VDO1_DPINTF>,
> + <&apmixedsys CLK_APMIXED_TVDPLL2>;
> + clock-names = "engine", "pixel", "pll";
> + status = "disabled";
> + };
> };
> };
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 1/4] arm64: dts: mt8195: Add dp-intf nodes
2022-09-15 8:13 ` AngeloGioacchino Del Regno
@ 2022-09-15 8:32 ` Bo-Chen Chen
0 siblings, 0 replies; 11+ messages in thread
From: Bo-Chen Chen @ 2022-09-15 8:32 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org
Cc: matthias.bgg@gmail.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-09-15 at 16:13 +0800, AngeloGioacchino Del Regno wrote:
> Il 15/09/22 09:58, Bo-Chen Chen ha scritto:
> > Add dp-intf0 and dp-intf1 nodes for MT8195.
> >
> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23
> > +++++++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index 905d1a90b406..93e6a106a9b8 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -2155,5 +2155,28 @@
> > clock-names = "apb", "smi", "gals";
> > power-domains = <&spm
> > MT8195_POWER_DOMAIN_VDOSYS1>;
> > };
> > +
> > + dp_intf0: dp-intf@1c015000 {
>
> Please keep the devicetree nodes ordered by mmio.
> dp_intf0 goes between mutex@1c016000 and larb@1c018000.
>
Hello Angelo,
Thanks for your review.
I think it should be merge@1c014000 and mutex@1c016000?
I will move dp-intf@1c015000 between them.
> > + status = "disabled";
>
> status = "disabled" across the entire mt8195.dtsi nodes is always at
> the end.
> Please keep consistency.
>
OK, I will modify this in next version.
BRs,
Bo-Chen
> > + compatible = "mediatek,mt8195-dp-intf";
> > + reg = <0 0x1c015000 0 0x1000>;
> > + interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + clocks = <&vdosys0 CLK_VDO0_DP_INTF0>,
> > + <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
> > + <&apmixedsys CLK_APMIXED_TVDPLL1>;
> > + clock-names = "engine", "pixel", "pll";
> > + };
> > +
> > + dp_intf1: dp-intf@1c113000 {
> > + compatible = "mediatek,mt8195-dp-intf";
> > + reg = <0 0x1c113000 0 0x1000>;
> > + interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + power-domains = <&spm
> > MT8195_POWER_DOMAIN_VDOSYS1>;
> > + clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
> > + <&vdosys1 CLK_VDO1_DPINTF>,
> > + <&apmixedsys CLK_APMIXED_TVDPLL2>;
> > + clock-names = "engine", "pixel", "pll";
> > + status = "disabled";
> > + };
> > };
> > };
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/4] arm64: dts: mt8195: Add dptx nodes
2022-09-15 7:58 [PATCH 0/4] Add dp-intf and dp nodes Bo-Chen Chen
2022-09-15 7:58 ` [PATCH 1/4] arm64: dts: mt8195: Add dp-intf nodes Bo-Chen Chen
@ 2022-09-15 7:58 ` Bo-Chen Chen
2022-09-15 8:14 ` AngeloGioacchino Del Regno
2022-09-15 7:58 ` [PATCH 3/4] arm64: dts: mediatek: cherry: Add dp-intf ports Bo-Chen Chen
2022-09-15 7:58 ` [PATCH 4/4] arm64: dts: mediatek: cherry: Add edptx and dptx support Bo-Chen Chen
3 siblings, 1 reply; 11+ messages in thread
From: Bo-Chen Chen @ 2022-09-15 7:58 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt
Cc: matthias.bgg, angelogioacchino.delregno, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Bo-Chen Chen
Add edptx and dptx nodes for MT8195.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 93e6a106a9b8..6f3f9bf3dc54 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1241,6 +1241,9 @@
reg = <0x189 0x2>;
bits = <7 5>;
};
+ dp_calibration: dp-data@1ac {
+ reg = <0x1ac 0x10>;
+ };
};
u3phy2: t-phy@11c40000 {
@@ -2178,5 +2181,27 @@
clock-names = "engine", "pixel", "pll";
status = "disabled";
};
+
+ edp_tx: edp-tx@1c500000 {
+ status = "disabled";
+ compatible = "mediatek,mt8195-edp-tx";
+ reg = <0 0x1c500000 0 0x8000>;
+ nvmem-cells = <&dp_calibration>;
+ nvmem-cell-names = "dp_calibration_data";
+ power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
+ interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
+ max-linkrate-mhz = <8100>;
+ };
+
+ dp_tx: dp-tx@1c600000 {
+ compatible = "mediatek,mt8195-dp-tx";
+ reg = <0 0x1c600000 0 0x8000>;
+ nvmem-cells = <&dp_calibration>;
+ nvmem-cell-names = "dp_calibration_data";
+ power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
+ interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ max-linkrate-mhz = <8100>;
+ };
};
};
--
2.18.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 2/4] arm64: dts: mt8195: Add dptx nodes
2022-09-15 7:58 ` [PATCH 2/4] arm64: dts: mt8195: Add dptx nodes Bo-Chen Chen
@ 2022-09-15 8:14 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 11+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-15 8:14 UTC (permalink / raw)
To: Bo-Chen Chen, robh+dt, krzysztof.kozlowski+dt
Cc: matthias.bgg, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Project_Global_Chrome_Upstream_Group
Il 15/09/22 09:58, Bo-Chen Chen ha scritto:
> Add edptx and dptx nodes for MT8195.
>
> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 93e6a106a9b8..6f3f9bf3dc54 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1241,6 +1241,9 @@
> reg = <0x189 0x2>;
> bits = <7 5>;
> };
> + dp_calibration: dp-data@1ac {
> + reg = <0x1ac 0x10>;
> + };
> };
>
> u3phy2: t-phy@11c40000 {
> @@ -2178,5 +2181,27 @@
> clock-names = "engine", "pixel", "pll";
> status = "disabled";
> };
> +
> + edp_tx: edp-tx@1c500000 {
> + status = "disabled";
> + compatible = "mediatek,mt8195-edp-tx";
> + reg = <0 0x1c500000 0 0x8000>;
> + nvmem-cells = <&dp_calibration>;
> + nvmem-cell-names = "dp_calibration_data";
> + power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
> + interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
> + max-linkrate-mhz = <8100>;
> + };
> +
> + dp_tx: dp-tx@1c600000 {
> + compatible = "mediatek,mt8195-dp-tx";
> + reg = <0 0x1c600000 0 0x8000>;
> + nvmem-cells = <&dp_calibration>;
> + nvmem-cell-names = "dp_calibration_data";
> + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
> + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
> + status = "disabled";
> + max-linkrate-mhz = <8100>;
max-linkrate-mhz should go before status.
> + };
> };
> };
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/4] arm64: dts: mediatek: cherry: Add dp-intf ports
2022-09-15 7:58 [PATCH 0/4] Add dp-intf and dp nodes Bo-Chen Chen
2022-09-15 7:58 ` [PATCH 1/4] arm64: dts: mt8195: Add dp-intf nodes Bo-Chen Chen
2022-09-15 7:58 ` [PATCH 2/4] arm64: dts: mt8195: Add dptx nodes Bo-Chen Chen
@ 2022-09-15 7:58 ` Bo-Chen Chen
2022-09-15 8:13 ` AngeloGioacchino Del Regno
2022-09-15 7:58 ` [PATCH 4/4] arm64: dts: mediatek: cherry: Add edptx and dptx support Bo-Chen Chen
3 siblings, 1 reply; 11+ messages in thread
From: Bo-Chen Chen @ 2022-09-15 7:58 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt
Cc: matthias.bgg, angelogioacchino.delregno, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Bo-Chen Chen
Add dp-intf0 and dp-intf1 ports.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
---
.../arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 9b62e161db26..303dc32c64dc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -120,6 +120,24 @@
};
};
+&dp_intf0 {
+ status = "okay";
+
+ port {
+ dp_intf0_out: endpoint {
+ };
+ };
+};
+
+&dp_intf1 {
+ status = "okay";
+
+ port {
+ dp_intf1_out: endpoint {
+ };
+ };
+};
+
&i2c0 {
status = "okay";
--
2.18.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 4/4] arm64: dts: mediatek: cherry: Add edptx and dptx support
2022-09-15 7:58 [PATCH 0/4] Add dp-intf and dp nodes Bo-Chen Chen
` (2 preceding siblings ...)
2022-09-15 7:58 ` [PATCH 3/4] arm64: dts: mediatek: cherry: Add dp-intf ports Bo-Chen Chen
@ 2022-09-15 7:58 ` Bo-Chen Chen
2022-09-15 8:13 ` AngeloGioacchino Del Regno
3 siblings, 1 reply; 11+ messages in thread
From: Bo-Chen Chen @ 2022-09-15 7:58 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt
Cc: matthias.bgg, angelogioacchino.delregno, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Bo-Chen Chen
- Add pinctrl for edptx and dptx.
- Add port for edptx and dptx.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
---
.../boot/dts/mediatek/mt8195-cherry.dtsi | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 303dc32c64dc..560103e29017 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -125,6 +125,7 @@
port {
dp_intf0_out: endpoint {
+ remote-endpoint = <&edp_in>;
};
};
};
@@ -134,6 +135,59 @@
port {
dp_intf1_out: endpoint {
+ remote-endpoint = <&dptx_in>;
+ };
+ };
+};
+
+&edp_tx {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&edptx_pins_default>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ edp_in: endpoint {
+ remote-endpoint = <&dp_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ edp_out: endpoint {
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+};
+
+&dp_tx {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&dptx_pin>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dptx_in: endpoint {
+ remote-endpoint = <&dp_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dptx_out: endpoint {
+ data-lanes = <0 1 2 3>;
+ };
};
};
};
@@ -497,6 +551,20 @@
};
};
+ edptx_pins_default: edptx-default-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>;
+ bias-pull-up;
+ };
+ };
+
+ dptx_pin: dptx-default-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>;
+ bias-pull-up;
+ };
+ };
+
i2c0_pins: i2c0-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
--
2.18.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 4/4] arm64: dts: mediatek: cherry: Add edptx and dptx support
2022-09-15 7:58 ` [PATCH 4/4] arm64: dts: mediatek: cherry: Add edptx and dptx support Bo-Chen Chen
@ 2022-09-15 8:13 ` AngeloGioacchino Del Regno
2022-09-15 8:33 ` Bo-Chen Chen
0 siblings, 1 reply; 11+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-15 8:13 UTC (permalink / raw)
To: Bo-Chen Chen, robh+dt, krzysztof.kozlowski+dt
Cc: matthias.bgg, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Project_Global_Chrome_Upstream_Group
Il 15/09/22 09:58, Bo-Chen Chen ha scritto:
> - Add pinctrl for edptx and dptx.
> - Add port for edptx and dptx.
>
The commit description is not great: explain why this board needs eDP/DP
(so, explain that eDP is connected to internal panel, DP for external display)
Thanks,
Angelo
> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 4/4] arm64: dts: mediatek: cherry: Add edptx and dptx support
2022-09-15 8:13 ` AngeloGioacchino Del Regno
@ 2022-09-15 8:33 ` Bo-Chen Chen
0 siblings, 0 replies; 11+ messages in thread
From: Bo-Chen Chen @ 2022-09-15 8:33 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org
Cc: matthias.bgg@gmail.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-09-15 at 16:13 +0800, AngeloGioacchino Del Regno wrote:
> Il 15/09/22 09:58, Bo-Chen Chen ha scritto:
> > - Add pinctrl for edptx and dptx.
> > - Add port for edptx and dptx.
> >
>
> The commit description is not great: explain why this board needs
> eDP/DP
> (so, explain that eDP is connected to internal panel, DP for external
> display)
>
> Thanks,
> Angelo
>
Hello Angelo,
OK, I will improve the commit message in next version.
BRs,
Bo-Chen
> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread