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Mon, 27 Mar 2023 12:12:45 -0700 (PDT) Date: Mon, 27 Mar 2023 22:12:42 +0300 From: Vladimir Oltean To: arinc9.unal@gmail.com Subject: Re: [PATCH net 4/7] net: dsa: mt7530: set both CPU port interfaces to PHY_INTERFACE_MODE_NA Message-ID: <20230327191242.4qabzrn3vtx3l2a7@skbuf> References: <20230326140818.246575-1-arinc.unal@arinc9.com> <20230326140818.246575-5-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230326140818.246575-5-arinc.unal@arinc9.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230327_121251_177872_3352D2DE X-CRM114-Status: GOOD ( 26.01 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Lunn , Ilya Lipnitskiy , =?utf-8?B?UmVuw6k=?= van Dorst , Eric Dumazet , erkin.bozoglu@xeront.com, Florian Fainelli , Russell King , Richard van Schagen , Jakub Kicinski , Paolo Abeni , Landen Chao , Richard van Schagen , Sean Wang , DENG Qingfang , Russell King , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org, AngeloGioacchino Del Regno , =?utf-8?B?QXLEsW7DpyDDnE5BTA==?= , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, "David S. Miller" Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Sun, Mar 26, 2023 at 05:08:15PM +0300, arinc9.unal@gmail.com wrote: > From: Arınç ÜNAL > > Set interfaces of both CPU ports to PHY_INTERFACE_MODE_NA. Either phylink > or mt7530_setup_port5() on mt7530_setup() will handle the rest. > > This is already being done for port 6, do it for port 5 as well. > > Fixes: 38f790a80560 ("net: dsa: mt7530: Add support for port 5") This is getting comical.. I think I'm putting too much energy in trying to understand the hidden meaning of this patch set. In include/linux/phy.h we have: typedef enum { PHY_INTERFACE_MODE_NA, In lack of other initializer, the first element of an enum gets the value 0 in C. Then, "priv" is allocated by this driver with devm_kzalloc(), which means that its entire memory is zero-filled. So priv->p5_interface and priv->p6_interface are already set to 0, or PHY_INTERFACE_MODE_NA. There is no code path between the devm_kzalloc() and the position in mt7530_setup() that would change the value of priv->p5_interface or priv->p6_interface from their value of 0 (PHY_INTERFACE_MODE_NA). For example, mt753x_phylink_mac_config() can only be called from phylink, after dsa_port_phylink_create() was called. But dsa_port_phylink_create() comes later than ds->ops->setup() - one comes from dsa_tree_setup_ports(), and the other from dsa_tree_setup_switches(). The movement of the priv->p6_interface assignment with a few lines earlier does not change anything relative to the other call sites which assign different values to priv->p6_interface, so there isn't any functional change there, either. So this patch is putting 0 into a variable containing 0, and claiming, through the presence of the Fixes: tag and the submission to the "net" tree, that it is a bug fix which should be backported to "stable". Can it be that you are abusing the meaning of a "bug fix", and that I'm trying too hard to take this patch set seriously? > Tested-by: Arınç ÜNAL > Signed-off-by: Arınç ÜNAL > --- > drivers/net/dsa/mt7530.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c > index 6d33c1050458..3deebdcfeedf 100644 > --- a/drivers/net/dsa/mt7530.c > +++ b/drivers/net/dsa/mt7530.c > @@ -2203,14 +2203,18 @@ mt7530_setup(struct dsa_switch *ds) > mt7530_rmw(priv, MT7530_TRGMII_RD(i), > RD_TAP_MASK, RD_TAP(16)); > > + /* Let phylink decide the interface later. If port 5 is used for phy > + * muxing, its interface will be handled without involving phylink. > + */ > + priv->p5_interface = PHY_INTERFACE_MODE_NA; > + priv->p6_interface = PHY_INTERFACE_MODE_NA; > + > /* Enable port 6 */ > val = mt7530_read(priv, MT7530_MHWTRAP); > val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; > val |= MHWTRAP_MANUAL; > mt7530_write(priv, MT7530_MHWTRAP, val); > > - priv->p6_interface = PHY_INTERFACE_MODE_NA; > - > /* Enable and reset MIB counters */ > mt7530_mib_reset(ds); > > -- > 2.37.2 >