[PATCH v4 9/9] ASoC: dt-bindings: mediatek,mt8188-afe: add audio properties

Trevor Wu
2023-05-10T03:56:23Z

Add apll1_d4 to clocks for switching the parent of top_a1sys_hp
dynamically and add property "mediatek,infracfg" for bus protection.

Because no mt8188 upstream dts exists, the change won't break anything.
In addition, apll2_d4, apll12_div4, top_a2sys and top_aud_iec are also
included in clocks, because these clocks are possibly used in the future.

Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
---
.../bindings/sound/mediatek,mt8188-afe.yaml | 30 +++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml
index 9e877f0d19fb..e6cb711ece77 100644
--- a/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml
+++ b/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml
@@ -29,6 +29,10 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle
description: The phandle of the mediatek topckgen controller

+ mediatek,infracfg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The phandle of the mediatek infracfg controller
+
power-domains:
maxItems: 1

@@ -52,6 +56,11 @@ properties:
- description: mux for i2si1_mck
- description: mux for i2si2_mck
- description: audio 26m clock
+ - description: audio pll1 divide 4
+ - description: audio pll2 divide 4
+ - description: clock divider for iec
+ - description: mux for a2sys clock
+ - description: mux for aud_iec

clock-names:
items:
@@ -73,6 +82,11 @@ properties:
- const: top_i2si1
- const: top_i2si2
- const: adsp_audio_26m
+ - const: apll1_d4
+ - const: apll2_d4
+ - const: apll12_div4
+ - const: top_a2sys
+ - const: top_aud_iec

mediatek,etdm-in1-cowork-source:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -144,6 +158,7 @@ required:
- resets
- reset-names
- mediatek,topckgen
+ - mediatek,infracfg
- power-domains
- clocks
- clock-names
@@ -162,6 +177,7 @@ examples:
resets = <&watchdog 14>;
reset-names = "audiosys";
mediatek,topckgen = <&topckgen>;
+ mediatek,infracfg = <&infracfg_ao>;
power-domains = <&spm 13>; //MT8188_POWER_DOMAIN_AUDIO
mediatek,etdm-in2-cowork-source = <2>;
mediatek,etdm-out2-cowork-source = <0>;
@@ -184,7 +200,12 @@ examples:
<&topckgen 78>, //CLK_TOP_I2SO2
<&topckgen 79>, //CLK_TOP_I2SI1
<&topckgen 80>, //CLK_TOP_I2SI2
- <&adsp_audio26m 0>; //CLK_AUDIODSP_AUDIO26M
+ <&adsp_audio26m 0>, //CLK_AUDIODSP_AUDIO26M
+ <&topckgen 132>, //CLK_TOP_APLL1_D4
+ <&topckgen 133>, //CLK_TOP_APLL2_D4
+ <&topckgen 183>, //CLK_TOP_APLL12_CK_DIV4
+ <&topckgen 84>, //CLK_TOP_A2SYS
+ <&topckgen 82>; //CLK_TOP_AUD_IEC>;
clock-names = "clk26m",
"apll1",
"apll2",
@@ -202,7 +223,12 @@ examples:
"top_i2so2",
"top_i2si1",
"top_i2si2",
- "adsp_audio_26m";
+ "adsp_audio_26m",
+ "apll1_d4",
+ "apll2_d4",
+ "apll12_div4",
+ "top_a2sys",
+ "top_aud_iec";
};

...
--
2.18.0