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([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:15:57 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Subject: [PATCH net-next 04/30] net: dsa: mt7530: improve comments regarding port 5 and 6 Date: Mon, 22 May 2023 15:15:06 +0300 Message-Id: <20230522121532.86610-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230522_051600_166811_990463B8 X-CRM114-Status: GOOD ( 12.99 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mithat.guner@xeront.com, Richard van Schagen , linux-kernel@vger.kernel.org, Richard van Schagen , =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , linux-mediatek@lists.infradead.org, Bartel Eerdekens , netdev@vger.kernel.org, erkin.bozoglu@xeront.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL There's no logic to numerically order the CPU ports. State the port number and its capability of being used as a CPU port instead. Remove the irrelevant PHY muxing information from mt7530_mac_port_get_caps(). Explain the supported MII modes instead. Remove the out of place PHY muxing information from mt753x_phylink_mac_config(). The function is for both the MT7530 and MT7531 switches but there's no PHY muxing on MT7531. These comments were gradually introduced with the commits below. ca366d6c889b ("net: dsa: mt7530: Convert to PHYLINK API") 38f790a80560 ("net: dsa: mt7530: Add support for port 5") 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding a new hardware") c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Arınç ÜNAL Acked-by: Daniel Golle --- drivers/net/dsa/mt7530.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 024b853f9558..b28d66a7c0b2 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2499,7 +2499,9 @@ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, config->supported_interfaces); break; - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + case 5: /* Port 5 which can be used as a CPU port supports rgmii with + * delays, mii, and gmii. + */ phy_interface_set_rgmii(config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); @@ -2507,7 +2509,9 @@ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, config->supported_interfaces); break; - case 6: /* 1st cpu port */ + case 6: /* Port 6 which can be used as a CPU port supports rgmii and + * trgmii. + */ __set_bit(PHY_INTERFACE_MODE_RGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_TRGMII, @@ -2527,14 +2531,17 @@ static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, config->supported_interfaces); break; - case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ + case 5: /* Port 5 which can be used as a CPU port supports rgmii with + * delays on MT7531BE, sgmii/802.3z on MT7531AE. + */ if (!priv->p5_sgmii) { phy_interface_set_rgmii(config->supported_interfaces); break; } fallthrough; - case 6: /* 1st cpu port supports sgmii/8023z only */ + case 6: /* Port 6 which can be used as a CPU port supports sgmii/802.3z. + */ __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_1000BASEX, @@ -2726,7 +2733,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, state->interface != PHY_INTERFACE_MODE_INTERNAL) goto unsupported; break; - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + case 5: /* Port 5, can be used as a CPU port. */ if (priv->p5_interface == state->interface) break; @@ -2736,7 +2743,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, if (priv->p5_intf_sel != P5_DISABLED) priv->p5_interface = state->interface; break; - case 6: /* 1st cpu port */ + case 6: /* Port 6, can be used as a CPU port. */ if (priv->p6_interface == state->interface) break; -- 2.39.2