From: Jason-JH.Lin <jason-jh.lin@mediatek.com>
To: Jassi Brar <jassisinghbrar@gmail.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Jeffrey Kardatzke <jkardatzke@google.com>,
Jason-ch Chen <jason-ch.chen@mediatek.com>,
Johnson Wang <johnson.wang@mediatek.com>,
"Jason-JH . Lin" <jason-jh.lin@mediatek.com>,
Singo Chang <singo.chang@mediatek.com>,
Nancy Lin <nancy.lin@mediatek.com>,
Shawn Sung <shawn.sung@mediatek.com>
Subject: [PATCH v2 4/9] soc: mailbox: Add cmdq_pkt_write_s_reg_value to support write value to reg
Date: Mon, 23 Oct 2023 12:37:46 +0800 [thread overview]
Message-ID: <20231023043751.17114-5-jason-jh.lin@mediatek.com> (raw)
In-Reply-To: <20231023043751.17114-1-jason-jh.lin@mediatek.com>
Add cmdq_pkt_write_s_reg_value to support write a value to a register.
It appends write_s command to the command buffer in a CMDQ packet,
ask GCE to excute a write instruction to write a value to a register
with low 16 bits physical address offset.
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 13 +++++++++++++
include/linux/soc/mediatek/mtk-cmdq.h | 11 +++++++++++
2 files changed, 24 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index 5194d66dfc0a..4be2a18a4a02 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -287,6 +287,19 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,
}
EXPORT_SYMBOL(cmdq_pkt_write_s_value);
+int cmdq_pkt_write_s_reg_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, u32 value)
+{
+ struct cmdq_instruction inst = {};
+
+ inst.op = CMDQ_CODE_WRITE_S;
+ inst.dst_t = CMDQ_REG_TYPE;
+ inst.reg_dst = high_addr_reg_idx;
+ inst.value = value;
+
+ return cmdq_pkt_append_command(pkt, inst);
+}
+EXPORT_SYMBOL(cmdq_pkt_write_s_reg_value);
+
int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,
u16 addr_low, u32 value, u32 mask)
{
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index ea4fadfb5443..4262594a0d18 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -207,6 +207,17 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,
int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,
u16 addr_low, u32 value, u32 mask);
+/**
+ * cmdq_pkt_write_s_reg_value() - append write_s command to the CMDQ packet which
+ * write value to a register with low address pa
+ * @pkt: the CMDQ packet
+ * @reg_idx: internal register ID which contains high address of pa
+ * @value: the specified target value
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_write_s_reg_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, u32 value);
+
/**
* cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
* @pkt: the CMDQ packet
--
2.18.0
next prev parent reply other threads:[~2023-10-23 4:38 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 4:37 [PATCH v2 0/9] Add CMDQ secure driver for SVP Jason-JH.Lin
2023-10-23 4:37 ` [PATCH v2 1/9] dt-bindings: gce: mt8195: Add CMDQ_SYNC_TOKEN_SECURE_THR_EOF event id Jason-JH.Lin
2023-10-23 7:47 ` Krzysztof Kozlowski
2023-10-23 7:49 ` Krzysztof Kozlowski
2023-10-24 16:21 ` Jason-JH Lin (林睿祥)
2023-10-25 6:26 ` Jason-JH Lin (林睿祥)
2023-10-25 7:03 ` Krzysztof Kozlowski
2023-10-25 7:36 ` Jason-JH Lin (林睿祥)
2023-10-23 8:08 ` Krzysztof Kozlowski
2023-10-25 6:28 ` Jason-JH Lin (林睿祥)
2023-10-23 4:37 ` [PATCH v2 2/9] dt-bindings: mailbox: Add property for CMDQ secure driver Jason-JH.Lin
2023-10-23 7:49 ` Krzysztof Kozlowski
2023-10-24 16:37 ` Jason-JH Lin (林睿祥)
2023-10-28 9:10 ` Krzysztof Kozlowski
2023-10-31 2:34 ` Jason-JH Lin (林睿祥)
2023-10-23 4:37 ` [PATCH v2 3/9] soc: mailbox: Add cmdq_pkt_logic_command to support math operation Jason-JH.Lin
2023-10-23 8:26 ` Fei Shao
2023-10-23 9:14 ` Fei Shao
2023-10-24 16:59 ` Jason-JH Lin (林睿祥)
2023-10-23 9:50 ` AngeloGioacchino Del Regno
2023-10-24 17:11 ` Jason-JH Lin (林睿祥)
2023-10-23 4:37 ` Jason-JH.Lin [this message]
2023-10-23 9:50 ` [PATCH v2 4/9] soc: mailbox: Add cmdq_pkt_write_s_reg_value to support write value to reg AngeloGioacchino Del Regno
2023-10-25 0:45 ` Jason-JH Lin (林睿祥)
2023-10-23 4:37 ` [PATCH v2 5/9] soc: mailbox: Add cmdq_pkt_finalize_loop to support looping cmd with irq Jason-JH.Lin
2023-10-23 9:50 ` AngeloGioacchino Del Regno
2023-10-25 0:55 ` Jason-JH Lin (林睿祥)
2023-10-23 4:37 ` [PATCH v2 6/9] mailbox: mediatek: Add CMDQ driver support for mt8188 Jason-JH.Lin
2023-10-23 9:41 ` Fei Shao
2023-10-25 6:33 ` Jason-JH Lin (林睿祥)
2023-10-23 9:50 ` AngeloGioacchino Del Regno
2023-10-23 10:14 ` AngeloGioacchino Del Regno
2023-10-25 0:58 ` Jason-JH Lin (林睿祥)
2023-10-23 4:37 ` [PATCH v2 7/9] mailbox: mediatek: Add secure CMDQ driver support for CMDQ driver Jason-JH.Lin
2023-10-23 10:47 ` Fei Shao
2023-10-25 2:08 ` Jason-JH Lin (林睿祥)
2023-10-23 4:37 ` [PATCH v2 8/9] mailbox: mediatek: Add CMDQ secure mailbox driver Jason-JH.Lin
2023-10-23 10:48 ` AngeloGioacchino Del Regno
2023-10-25 6:20 ` Jason-JH Lin (林睿祥)
2023-11-06 6:53 ` CK Hu (胡俊光)
2023-11-06 13:07 ` Jason-JH Lin (林睿祥)
2023-10-23 4:37 ` [PATCH v2 9/9] arm64: dts: mediatek: mt8195: Add CMDQ secure driver support for gce0 Jason-JH.Lin
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