Re: 回复: [PATCH] PCI: mediatek-gen3: Avoid PCIe resetting for Airoha EN7581 SoC

AngeloGioacchino Del Regno
2024-09-23T11:29:27Z

Il 23/09/24 12:06, Hui Ma (马慧) ha scritto:
> Hi Angelo，
>
> EN7581 doesn't support pulling up/down PERST by bit3 of PCIe MAC register 0x148(PCIE_RST_CTRL_REG).
>
> EN7581 toggle PERST in clk_bulk_enable function called by mtk_pcie_en7581_power_up function.
>

Hello Hui,
please don't top post.

Anyway, are those bits unexistant on EN7581, or are those used for different
functions?

If those do not exist, and setting those bits will not produce adverse effects,
it'd be possible to avoid creating a different codepath and just add a comment
saying that the setting has no effect on Airoha EN7581.

Regards,
Angelo

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> -----邮件原件-----
> 发件人: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> 发送时间: 2024年9月23日 17:42
> 收件人: Lorenzo Bianconi <lorenzo@kernel.org>; Ryder Lee <Ryder.Lee@mediatek.com>; Jianjun Wang (王建军) <Jianjun.Wang@mediatek.com>; Lorenzo Pieralisi <lpieralisi@kernel.org>; Krzysztof Wilczyński <kw@linux.com>; Rob Herring <robh@kernel.org>; Bjorn Helgaas <bhelgaas@google.com>; Matthias Brugger <matthias.bgg@gmail.com>
> 抄送: Christian Marangi <ansuelsmth@gmail.com>; linux-pci@vger.kernel.org; linux-mediatek@lists.infradead.org; linux-arm-kernel@lists.infradead.org; upstream <upstream@airoha.com>; Hui Ma (马慧) <Hui.Ma@airoha.com>
> 主题: Re: [PATCH] PCI: mediatek-gen3: Avoid PCIe resetting for Airoha EN7581 SoC
>
>
>
> Il 20/09/24 10:26, Lorenzo Bianconi ha scritto:
>
>> The PCIe controller available on the EN7581 SoC does not support reset
>
>> via the following lines:
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>> - PCIE_MAC_RSTB
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>> - PCIE_PHY_RSTB
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>> - PCIE_BRG_RSTB
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>> - PCIE_PE_RSTB
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>>
>
>> Introduce the reset callback in order to avoid resetting the PCIe port
>
>> for Airoha EN7581 SoC.
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>>
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>
> EN7581 doesn't support pulling up/down PERST#?!
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> That looks definitely odd, as that signal is part of the PCI-Express CEM spec.
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> Besides, there's another PERST# assertion at mtk_pcie_suspend_noirq()...
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> Cheers,
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> Angelo
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>> Tested-by: Hui Ma <hui.ma@airoha.com<mailto:hui.ma@airoha.com>>
>
>> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org<mailto:lorenzo@kernel.org>>
>
>> ---
>
>> drivers/pci/controller/pcie-mediatek-gen3.c | 44 ++++++++++++++++++-----------
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>> 1 file changed, 28 insertions(+), 16 deletions(-)
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>>
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>> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
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>> b/drivers/pci/controller/pcie-mediatek-gen3.c
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>> index 5c19abac74e8..9cea67e92d98 100644
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>> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
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>> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
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>> @@ -128,10 +128,12 @@ struct mtk_gen3_pcie;
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>> /**
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>> * struct mtk_gen3_pcie_pdata - differentiate between host generations
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>> * @power_up: pcie power_up callback
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>> + * @reset: pcie reset callback
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>> * @phy_resets: phy reset lines SoC data.
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>> */
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>> struct mtk_gen3_pcie_pdata {
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>> int (*power_up)(struct mtk_gen3_pcie *pcie);
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>> + void (*reset)(struct mtk_gen3_pcie *pcie);
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>> struct {
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>> const char *id[MAX_NUM_PHY_RESETS];
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>> int num_resets;
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>> @@ -373,6 +375,28 @@ static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie)
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>> writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
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>> }
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>>
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>> +static void mtk_pcie_reset(struct mtk_gen3_pcie *pcie) {
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>> + u32 val;
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>> +
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>> + /* Assert all reset signals */
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>> + val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
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>> + val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
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>> + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
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>> +
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>> + /*
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>> + * Described in PCIe CEM specification sections 2.2 (PERST# Signal)
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>> + * and 2.2.1 (Initial Power-Up (G3 to S0)).
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>> + * The deassertion of PERST# should be delayed 100ms (TPVPERL)
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>> + * for the power and clock to become stable.
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>> + */
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>> + msleep(100);
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>> +
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>> + /* De-assert reset signals */
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>> + val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
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>> + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); }
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>> +
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>> static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
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>> {
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>> struct resource_entry *entry;
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>> @@ -402,22 +426,9 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
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>> val |= PCIE_DISABLE_DVFSRC_VLT_REQ;
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>> writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG);
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>>
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>> - /* Assert all reset signals */
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>> - val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
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>> - val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
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>> - writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
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>> -
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>> - /*
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>> - * Described in PCIe CEM specification sections 2.2 (PERST# Signal)
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>> - * and 2.2.1 (Initial Power-Up (G3 to S0)).
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>> - * The deassertion of PERST# should be delayed 100ms (TPVPERL)
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>> - * for the power and clock to become stable.
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>> - */
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>> - msleep(100);
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>> -
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>> - /* De-assert reset signals */
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>> - val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
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>> - writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
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>> + /* Reset the PCIe port if requested by the hw */
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>> + if (pcie->soc->reset)
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>> + pcie->soc->reset(pcie);
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>>
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>> /* Check if the link is up or not */
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>> err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val, @@
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>> -1207,6 +1218,7 @@ static const struct dev_pm_ops mtk_pcie_pm_ops = {
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>>
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>> static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8192 = {
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>> .power_up = mtk_pcie_power_up,
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>> + .reset = mtk_pcie_reset,
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>> .phy_resets = {
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>> .id[0] = "phy",
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>> .num_resets = 1,
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>>
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>> ---
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>> base-commit: f2024903cb387971abdbc6398a430e735a9b394c
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>> change-id: 20240920-pcie-en7581-rst-fix-8161658c13c4
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>>
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>> Best regards,
>
>