From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94CD7C2D0CD for ; Thu, 15 May 2025 10:22:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=u/+0dwJEixmbwzYEuP2QfiyZsxMQa+r+ZFjKbyOO3Rs=; b=jODAKKfQmDsm97WSWezvBIoH9x p6uvEO+Zv/TRpktgfOPzn+8hsZgZgi3OYcfeiX7Q2bQsATIf6DclqsPa16Q9MuhSqGuK6BvEqcOuF jP8LQXanJ8wpNqzp7qORKnlaA+9CN1d/zcrgN8OPGHfgc7Y8AhqSrzvjSB6mUPXVcYLvQqfhXSBN9 fTSfrMqDj/dLgW8Kj3DaAmaSgDpEZMKm43EpaqzC+lNtqKQ7eyKSFuPngO2Mprif/X7KHdZVByHV1 mQI0lMklA2aaHZIj7SAwtlAMLDF7ullOqcLgQp4/njTmmiX088KREj8j4WZv6Fn0x0YNADdFXcgBA tflLfxeQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uFVjF-00000000HSj-1UpH; Thu, 15 May 2025 10:22:17 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uFVEU-00000000DYX-3TeC; Thu, 15 May 2025 09:50:32 +0000 X-UUID: e62e0774316f11f08d385d50fb11b32d-20250515 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=u/+0dwJEixmbwzYEuP2QfiyZsxMQa+r+ZFjKbyOO3Rs=; b=pDRCgd+AohafdBjCw9ogFIfIdjzFx5Q4khv2/BxTx8+VEhYluKLachaLJ3LSdWxNtdbvv1K6ItCFsxW5fq3TEZLZ1rSlQRzSBm3E7pid0NXoWjj2IBkwlC/W4HljzShn6+GcoCSOjCQGk8J+7VqsNXEOdTDqIkG6stcIn0Svb2Q=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1,REQID:2e7df52f-e8c6-45ee-905c-9ccbd05804ab,IP:0,UR L:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:-5 X-CID-META: VersionHash:0ef645f,CLOUDID:b3e504c0-eade-4d5b-9f81-31d7b5452436,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: e62e0774316f11f08d385d50fb11b32d-20250515 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1932495470; Thu, 15 May 2025 02:35:12 -0700 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Thu, 15 May 2025 17:35:09 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Thu, 15 May 2025 17:35:09 +0800 From: paul-pl.chen To: , , , , Subject: [PATCH v3 11/17] drm/mediatek: drm/mediatek: Export OVL ignore pixel alpha function Date: Thu, 15 May 2025 17:34:23 +0800 Message-ID: <20250515093454.1729720-12-paul-pl.chen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com> References: <20250515093454.1729720-1-paul-pl.chen@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250515_025030_876508_2B3D072C X-CRM114-Status: GOOD ( 13.61 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, xiandong.wang@mediatek.com, jason-jh.lin@mediatek.com, singo.chang@mediatek.com, treapking@chromium.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, paul-pl.chen@mediatek.com, nancy.lin@mediatek.com, linux-mediatek@lists.infradead.org, sunny.shen@mediatek.com, p.zabel@pengutronix.de, sirius.wang@mediatek.com, matthias.bgg@gmail.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Nancy Lin For the new BLENDER component, the OVL ignore pixel alpha logic should be exported as a function and reused it. Signed-off-by: Nancy Lin Signed-off-by: Paul-pl Chen --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 24 ++++++++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_disp_ovl.h | 1 + 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index a516b7c82b5a..747898a574da 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -211,6 +211,23 @@ void mtk_ovl_disable_vblank(struct device *dev) writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN); } +bool mtk_ovl_is_ignore_pixel_alpha(struct mtk_plane_state *state, unsigned int blend_mode) +{ + if (!state->base.fb) + return false; + /* + * Although the alpha channel can be ignored, CONST_BLD must be enabled + * for XRGB format, otherwise OVL will still read the value from memory. + * For RGB888 related formats, whether CONST_BLD is enabled or not won't + * affect the result. Therefore we use !has_alpha as the condition. + */ + + if (blend_mode == DRM_MODE_BLEND_PIXEL_NONE || !state->base.fb->format->has_alpha) + return true; + + return false; +} + u32 mtk_ovl_get_blend_modes(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); @@ -539,7 +556,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, unsigned int rotation = pending->rotation; unsigned int offset = (pending->y << 16) | pending->x; unsigned int src_size = (pending->height << 16) | pending->width; - unsigned int blend_mode = state->base.pixel_blend_mode; + unsigned int blend_mode = mtk_ovl_get_blend_mode(state, ovl->data->blend_modes); unsigned int ignore_pixel_alpha = 0; unsigned int con; @@ -557,7 +574,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, * For blend_modes supported SoCs, always enable alpha blending. * For blend_modes unsupported SoCs, enable alpha blending when has_alpha is set. */ - if (blend_mode || state->base.fb->format->has_alpha) + if (state->base.pixel_blend_mode || state->base.fb->format->has_alpha) con |= OVL_CON_AEN; } @@ -584,6 +601,9 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CON(idx)); + + if (mtk_ovl_is_ignore_pixel_alpha(state, blend_mode)) + ignore_pixel_alpha = OVL_CONST_BLEND; mtk_ddp_write_relaxed(cmdq_pkt, pitch_lsb | ignore_pixel_alpha, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx)); mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h index 3f7d7d54479d..431567538eb5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h @@ -20,6 +20,7 @@ extern const u32 mt8195_ovl_formats[]; extern const size_t mt8195_ovl_formats_len; bool mtk_ovl_is_10bit_rgb(unsigned int fmt); +bool mtk_ovl_is_ignore_pixel_alpha(struct mtk_plane_state *state, unsigned int blend_mode); unsigned int mtk_ovl_get_blend_mode(struct mtk_plane_state *state, unsigned int blend_modes); unsigned int mtk_ovl_fmt_convert(unsigned int fmt, unsigned int blend_mode, bool fmt_rgb565_is_0, bool color_convert, -- 2.45.2